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[libreriscv.git] / Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn

diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index c01b4b04202834fa43adfbe718cb8b4c696dcb67..ca8055d81a8a102d09c14e9ef3ccf24c16a0fc71 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -1,33 +1,10 @@
-# Comparative analysis of Andes Packed ISA proposal vs RVP Harmonised (with RV Vector spec)
+# Comparative analysis of Andes Packed ISA proposal vs Harmonised RVP
 
-## Proposed Harmonised RVP vector op instruction encoding
-
-Register x 2 -> register operations:
-
-| 31 30 29 28 27 26 | 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
-| ----------------- | --  | -------------- | -------------- | -- | ----- | ----------- | ------------- |
-| func_6            | 0   | rs2            | rs1            | 0  | mm    | rd1         | VOP opcode    |
-
-Immediate + register -> register operations:
-
-| 31 30 29 | 28 27 26 | 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
-| -------- | -------- | --  | -------------- | -------------- | -- | ----- | ----------- | ------------- |
-| func_3   | imm[7:5] | 1   | imm[4:0]       | rs1            | 0  | mm    | rd1         | VOP opcode    |
+Harmonised RVP is a proposal to provide SIMD functionality comparable to the Andes Packed SIMD ISA, but in a manner that is forwards compatible ("harmonised") with the RV Vector specification.
 
-Register x 3 -> register operations:
+An example use case is a string copy operation - using Harmonised RVP, binary code using integer register based SIMD to copy a string of bytes can also execute (unchanged) on a full RV Vector processor and use the dedicated vector unit to copy string.  The is also upwards compatibility between RV32 and RV64 SIMD using this same approach.
 
-| 31 30 29 28 27 | 26 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
-| ----------------------- | -------------- | -------------- | -- | ----- | ----------- | ------------- |
-| rs3            | func_2 | rs2            | rs1            | 1  | mm    | rd1         | VOP opcode    |
-
-Values for mm field (bits 12:13 above):
-
-* mm = 00 -> use current global saturation or rounding, no mask
-* mm = 00 -> force saturation or rounding for this instruction only
-* mm = 10 -> use v1 as predicate mask
-* mm = 11 -> use ~v1 as predicate mask
-
-## Register file
+## Register file comparison
 
 The default Harmonised RVP GPR register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16].
 In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT8 or INT16 vector operations
@@ -71,6 +48,33 @@ In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT
 | v31                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
 
 
+## Proposed Harmonised RVP vector op instruction encoding
+
+Register x 2 -> register operations:
+
+| 31 30 29 28 27 26 | 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
+| ----------------- | --  | -------------- | -------------- | -- | ----- | ----------- | ------------- |
+| func_6            | 0   | rs2            | rs1            | 0  | mm    | rd1         | VOP opcode    |
+
+Immediate + register -> register operations:
+
+| 31 30 29 | 28 27 26 | 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
+| -------- | -------- | --  | -------------- | -------------- | -- | ----- | ----------- | ------------- |
+| func_3   | imm[7:5] | 1   | imm[4:0]       | rs1            | 0  | mm    | rd1         | VOP opcode    |
+
+Register x 3 -> register operations:
+
+| 31 30 29 28 27 | 26 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
+| ----------------------- | -------------- | -------------- | -- | ----- | ----------- | ------------- |
+| rs3            | func_2 | rs2            | rs1            | 1  | mm    | rd1         | VOP opcode    |
+
+Values for mm field (bits 12:13 above):
+
+* mm = 00 -> no predicate mask, and use current global saturation / rounding settings
+* mm = 00 -> no predicate mask, and force saturation or rounding for this instruction only
+* mm = 10 -> use v1 as predicate mask, and use global saturation / rounding settings
+* mm = 11 -> use ~v1 as predicate mask, and use global saturation / rounding settings
+
 ## 16-bit Arithmetic
 
 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |