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[libreriscv.git] / Documentation / SOC / index.mdwn

diff --git a/Documentation/SOC/index.mdwn b/Documentation/SOC/index.mdwn
index 4b8873f76d279a4c7b716a27c71aa5d2a9d47049..4f1b4c30012e707650145e4427604f513b382d74 100644 (file)
--- a/Documentation/SOC/index.mdwn
+++ b/Documentation/SOC/index.mdwn
@@ -73,3 +73,14 @@ This also demonstrates one of the design aspects taken in this project: to
 advanced dynamically generated HDL, rather than (as done with MyHDL)
 limit python code to a subset of its full capabilities.
 
+The CSV Files are loaded by
+[power_decoder.py](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder.py;hb=HEAD)
+and are usedto construct a hierarchical cascade of switch statements.  The original code came from
+[microwatt](https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl)
+where the original hardcoded cascade can be seen.
+
+The docstring for power_decoder.py gives mire details: each levrl in the hierarchy, just as in the original decode1.vhdl, will take slices of the instruction bitpattern, match against it, and if successful will continue with further subdecoders until a line is met that contains the Operand Information (a PowerOp) exactly as shown at the top of this page.
+
+In this way, different sections of the instruction are successively decoded (major opcode, then minor opcode, then sub-patterns under those) until the required instruction is fully recognised, and the hierarchical cascade of switch patterns results in a flat interpretation being produced that is useful internally. 
+
+