## Original Instructions
-lkcl:
-
-
-> the JTAG TAP interface on the *FPGA* is hard-coded silicon.
-
-> the JTAG TAP interface connected on the processor and soft-implemented
-> *by* the FPGA is likely completely inaccessible until someone
-> allocates pins to "jtag_tdi/tdo/tms/tck" in the litex config.
->
-> which means: someone's going to have to to through this file:
-> <https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/ulx3s.py#L72>
-> (which defines the pin allocations)
->
-> and in this file do some Voodoo Magic on this file's TestSoC:
-> <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ulx3s85f.py;hb=HEAD>
->
-> similar to these four lines:
-> <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=4279effcffe2fbf15f877e9b2a1b76beab248dac;hb=HEAD#l460>
->
-> but instead doing something like... err....
->
-> gpio0_pads = platform.reqiest("gpio", 0) # because back in ulx3s.py there's gpio 0, 1, and 2
->
-> self.comb += self.cpu.jtag_tck.eq(gpio0_pads.p) # because again back in that file there are 2 pins, one named "p", one named "n"
->
-> self.comb += self.cpu.jtag_tms.eq(gpio0_pads.n) # etc.
->
-> and then request gpio1 for the other 2 pins
->
-> theeeen you'll need to go back to that ulx3s.py litex platform file,
-> look up the pin names B11, C11, A10, A11, and find out what the hell
-> they are, whether they're suitable for use.
->
-> if they are, then great! these are what you wire up the STLINKv2 to,
-> according to what you decided to connect to just above.
->
-> but for god's sake do not get this wrong, such as driving an input as
-> an output or vice-versa, or wiring up 5.0V to GND with those
-> jumper-cables.
->
-> do *NOT* randomly upload and power up the ulx3s until this has been
-> THOROUGHLY triple-checked. or, you are entirely free to not bother
-> and to end up learning the hard way by destroying the FPGA.
+See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
+
+TODO checklist based on above
+
+| Done? | Checklist Step |
+|---------|-------------|
+| | For god's sake do not get this wrong |
+| | ***DO NOT*** drive an input as an output or vice-versa |
+| | ***DO NOT*** wire up 5.0V to GND with the jumper-cables |
+| | ***DO NOT*** randomly upload and power up the FPGA until this has been ***THOROUGHLY*** triple-checked |
+| | If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
## Connecting the dots:
## Images of wires on FPGA and on STLINKV2
-[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="400x" ]]
+Image of JTAG jumper wire connections on ULX3S FPGA side
+
+[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]]
+
+Image of JTAG jumper wire connections on STLINKV2 side
+
+(same orientation as JTAG pinout documentation)
+
+[[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]
+
+Image of JTAG jumper wire connections on STLINKV2 side
-## Questions
+(opposite orientation as JTAG pinout documentation,
-Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance? Should we be using the CLK labeled pins specifically for JTAG or specifically avoid using them for JTAG?
+same orientation as 'ST' text on STLINKV2 device)
-Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
+[[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]
# STLinkV2 connector
| X3 pin # | FPGA IO PAD | STLinkv2 |Wire Colour|
|-------------|-------------|----------------|-----------|
-|1 GND | GND | GND | Black |
-|2 NC |NOT CONNECTED| NOT CONNECTED | NC |
-|3 +2V5 | 2.5V supply | 2 (MCU VDD) | Red |
+|1 GND | GND | 4 (GND) | Black |
+|2 NC | NC | NC | NC |
+|39 +3.3V | 3.3V supply | 2 (MCU VDD) | Red |
|4 IO29 | B19 | 5 (TDI) | Green |
|5 IO30 | B12 | 7 (TMS) | Blue |
|6 IO31 | B9 | 9 (TCK) | White |
projects / libreriscv.git / blobdiff