## Original Instructions
-lkcl:
-
-
-> the JTAG TAP interface on the *FPGA* is hard-coded silicon.
-
-> the JTAG TAP interface connected on the processor and soft-implemented
-> *by* the FPGA is likely completely inaccessible until someone
-> allocates pins to "jtag_tdi/tdo/tms/tck" in the litex config.
->
-> which means: someone's going to have to to through this file:
-> <https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/ulx3s.py#L72>
-> (which defines the pin allocations)
->
-> and in this file do some Voodoo Magic on this file's TestSoC:
-> <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ulx3s85f.py;hb=HEAD>
->
-> similar to these four lines:
-> <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=4279effcffe2fbf15f877e9b2a1b76beab248dac;hb=HEAD#l460>
->
-> but instead doing something like... err....
->
-> gpio0_pads = platform.reqiest("gpio", 0) # because back in ulx3s.py there's gpio 0, 1, and 2
->
-> self.comb += self.cpu.jtag_tck.eq(gpio0_pads.p) # because again back in that file there are 2 pins, one named "p", one named "n"
->
-> self.comb += self.cpu.jtag_tms.eq(gpio0_pads.n) # etc.
->
-> and then request gpio1 for the other 2 pins
->
-> theeeen you'll need to go back to that ulx3s.py litex platform file,
-> look up the pin names B11, C11, A10, A11, and find out what the hell
-> they are, whether they're suitable for use.
->
-> if they are, then great! these are what you wire up the STLINKv2 to,
-> according to what you decided to connect to just above.
->
-> but for god's sake do not get this wrong, such as driving an input as
-> an output or vice-versa, or wiring up 5.0V to GND with those
-> jumper-cables.
->
-> do *NOT* randomly upload and power up the ulx3s until this has been
-> THOROUGHLY triple-checked. or, you are entirely free to not bother
-> and to end up learning the hard way by destroying the FPGA.
+See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
+
+Checklist based on above
+
+* For god's sake make sure you get this right, ***TRIPLE*** check everything.
+
+* ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
+
+* ***DO*** make sure to ***only*** wire up 5.0V to 5.0V and to ***only*** wire up GND to GND with the jumper-cables.
+
+* ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
+
+If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
+
+To start we have to ensure we have a safe set up.
+
+| Checklist Step |
+|----------------|
+| Ensure power is disconnected from FPGA |
+| Ensure STLINKV2 USB is disconnected |
+| Ensure FPGA USB is disconnected |
+
+Now lets review all of the relevant material on this page before we begin the wiring process.
+
+| Checklist Step |
+|----------------|
+| Review the STLINKv2 Connector diagram and table |
+| Review the connections table for your model of fpga |
+| Ensure the orientation of the FPGA and STLINKv2 match that of the images and diagrams on this page |
+
+Next we will wire up the STLINKv2 and our FPGA in three separate stages.
+
+* First attaching one end of a jumper cable to each necessary header pin on the STLINKv2.
+
+* Then we will attach the end of a new jumper cable to each male header pin on the FPGA. Finally, we will connect the wires from the STLINKv2 to the wires from the FPGA by matching the colours of the wires. This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of each of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
+
+We will wire each of the pins on the the STLINKv2 according to the diagrams, tables, and images on this page.
+
+| Action | Colour | Pin # | Pin Name |
+|--------|--------|-------|----------|
+| Attach | Red | 2 | VREF |
+| Attach | Black | 4 | GND |
+| Attach | Green | 5 | TDI |
+| Attach | Blue | 7 | TMS |
+| Attach | White | 9 | TCK |
+| Attach | Yellow | 13 | TDO |
+
+Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
+
+Follow this section if you have the ULX3S FPGA:
+
+| Action | Colour | Pin # | Pin Name |
+|--------|--------|-------|----------|
+| Attach | Red | 2 | VREF |
+| Attach | Black | 4 | GND |
+| Attach | Green | 5 | TDI |
+| Attach | Blue | 6 | TMS |
+| Attach | White | 7 | TCK |
+| Attach | Yellow | 8 | TDO |
+
+Follow this section if you have the Versa ECP5 FPGA:
+
+| Action | Colour | X3 Pin # | Pin Name |
+|--------|--------|----------|----------|
+| Attach | Red | 39 | VREF |
+| Attach | Black | 1 | GND |
+| Attach | Green | 4 | TDI |
+| Attach | Blue | 5 | TMS |
+| Attach | White | 6 | TCK |
+| Attach | Yellow | 7 | TDO |
+
+Final steps for both FPGA boards:
+
+| Checklist Step |
+|----------------|
+| Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **THREE** times |
+| ***lckl*** check for ground loops? |
+
+
+Finally, we will connect the jumper cables of the same colour from STLINKv2 and the FPGA.
+
+| Checklist Step |
+|----------------|
+| Attach the ends of the **RED** jumper cables |
+| Attach the ends of the **BLACK** jumper cables |
+| Attach the ends of the **GREEN** jumper cables |
+| Attach the ends of the **BLUE** jumper cables |
+| Attach the ends of the **WHITE** jumper cables |
+| Attach the ends of the **YELLO** jumper cables |
## Connecting the dots:
## Images of wires on FPGA and on STLINKV2
-[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="400x" ]]
+Image of JTAG jumper wire connections on ULX3S FPGA side
+
+[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]]
+
+Image of JTAG jumper wire connections on STLINKV2 side
+
+(same orientation as JTAG pinout documentation)
+
+[[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]
+
+Image of JTAG jumper wire connections on STLINKV2 side
-## Questions
+(opposite orientation as JTAG pinout documentation,
-Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance? Should we be using the CLK labeled pins specifically for JTAG or specifically avoid using them for JTAG?
+same orientation as 'ST' text on STLINKV2 device)
-Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
+[[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]
# STLinkV2 connector
| X3 pin # | FPGA IO PAD | STLinkv2 |Wire Colour|
|-------------|-------------|----------------|-----------|
+|39 +3.3V | 3.3V supply | 2 (MCU VDD) | Red |
|1 GND | GND | 4 (GND) | Black |
-|2 NC | NC | NC | NC |
-|3 +2V5 | 2.5V supply | 2 (MCU VDD) | Red |
|4 IO29 | B19 | 5 (TDI) | Green |
|5 IO30 | B12 | 7 (TMS) | Blue |
|6 IO31 | B9 | 9 (TCK) | White |
projects / libreriscv.git / blobdiff