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[libreriscv.git] / HDL_workflow / ECP5_FPGA.mdwn

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index ab8005be9e6eb53febb4d20ef0685ca36bc26b7c..fad903c149e0ca9025d973b9bb26db518a32bf69 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -1,11 +1,26 @@
 # ULX3S JTAG Connection with ft232r
 
+Note: this page is for connecting a *secondary* JTAG connection to
+the Libre-SOC Core, in order to test the actual HDL implementation
+of JTAG.  "Normal" JTAG documentation instructs you how to connect
+to the **FPGA** hard-macro JTAG port (in some fashion).  Whilst the
+FPGA has a JTAG port as a hard-macro these instructions do **not**
+apply to that: they apply **specifically** to actual implementation
+in HDL of a JTAG TAP interface suitable for deployment on an ASIC,
+and, consequently, in order to test that, four GPIO pads had to be
+picked to bring those signals out.  These instructions describe how
+to correctly wire up an FT232r to connect to those four GPIO pads.
+
 Cross referenced with:
 
 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
 
 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
 
+<https://www.amazon.co.uk/DSD-TECH-adapter-FT232RL-Compatible/dp/B07BBPX8B8/ref=sr_1_11?dchild=1&keywords=ft232&qid=1632498288&s=amazon-devices&sr=1-11>
+
+<https://www.amazon.co.uk/Elegoo-120pcs-Multicolored-Breadboard-arduino-colorful/dp/B01EV70C78/>
+
 ## Original Instructions
 
 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
@@ -199,33 +214,21 @@ static int nsysrst_gpio = 6;
 ```
 
 ```from ft232 usb to 6 pin female header manual
- _________________________
-| Pin # | Name |  Colour  |
-|-------|------|----------|
-|   1   | GND  |  Black   |
-|   2   | CTS  |  Brown   |
-|   3   | VCC  |  Red     |
-|   4   | TXD  |  Orange  |
-|   5   | RXD  |  Yellow  |
-|   6   | RTS  |  Green   |
-|_______|______|__________|
-```
 
 ft232 pin and wire colour table converted to jtag signal names:
 
 ```
- _________________________
-| Pin # | Name |  Colour  |
-|-------|------|----------|
-|   1   | GND  |  Black   |
-|   2   | TMS  |  Brown   |
-|   3   | VCC  |  Red     |
-|   4   | TCK  |  Orange  |
-|   5   | TDI  |  Yellow  |
-|   6   | TDO  |  Green   |
-|_______|______|__________|
+|-------|------|--------|----------|
+| Pin # | JTAG |  FT232 | Colour   |
+|-------|------|--------|----------|
+|   1   | VCC  | VCC    |  Red     |
+|   2   | GND  | GND    |  Black   |
+|   3   | TCK  | TXD    |  White   |
+|   4   | TDI  | RXD    |  Green   |
+|   5   | TDO  | RTS    |  Yellow  |
+|   6   | TMS  | CTS    |  Blue    |
+|-------|------|--------|----------|
 ```
-
 Proposed FPGA External Pin to ft232r JTAG pin connections:
 
 ```
@@ -239,10 +242,10 @@ Proposed FPGA External Pin to ft232r JTAG pin connections:
 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    3 (VCC)     |    Red    |
 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 |4            |-|(GND)|    NONE     |     GND     |    1 (GND)     |   Black   |
-|5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (TDI)     |   Yellow  |
-|6 (J1_5+)    |   0   |     B11     |    gp[0]    |    2 (TMS)     |   Brown   |
-|7 (J1_7-)    |   1   |     A11     |    gn[1]    |    4 (TCK)     |   Orange  |
-|8 (J1_7+)    |   1   |     A10     |    gp[1]    |    6 (TDO)     |   Green   |
+|5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (TDI)     |   Green   |
+|6 (J1_5+)    |   0   |     B11     |    gp[0]    |    2 (TMS)     |   Blue    |
+|7 (J1_7-)    |   1   |     A11     |    gn[1]    |    4 (TCK)     |   White   |
+|8 (J1_7+)    |   1   |     A10     |    gp[1]    |    6 (TDO)     |   Yellow  |
 |_____________|_______|_____________|_____________|________________|___________|
 ```
 
@@ -262,8 +265,8 @@ and therefore have no value are marked with 'NOT'
 |                                                         |
 |(3 VCC) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT    |
 |(1 GND) black   [GND] 4  | -| |  3   NOT   NOT    NOT    |
-|(2 TMS) brown   [GP0] 6  |  0 |  5  [GN0] yellow (5 TDI) |
-|(6 TDO) green   [GP1] 8  |  1 |  7  [GN1] orange (4 TCK) |
+|(2 TMS) Blue    [GP0] 6  |  0 |  5  [GN0] Green  (5 TDI) |
+|(6 TDO) Yellow  [GP1] 8  |  1 |  7  [GN1] White  (4 TCK) |
 |_________________________________________________________|
 ```
 
@@ -285,14 +288,14 @@ Colour markings on ft232r side:
 
 Table of connections:
 
-| X3  pin #   | FPGA IO PAD |  ft232r   |Wire Colour|
-|-------------|-------------|-----------|-----------|
-|   39 +3.3V  | 3.3V supply |  3 (VCC)  |   Red     |
-|    1 GND    |     GND     |  1 (GND)  |   Black   |
-|    4 IO29   |     B19     |  5 (TDI)  |   Yellow  |
-|    5 IO30   |     B12     |  2 (TMS)  |   Brown   |
-|    6 IO31   |     B9      |  4 (TCK)  |   Orange  |
-|    7 IO32   |     E6      |  6 (TDO)  |   Green   |
+| X3  pin #   | FPGA IO PAD |  Function | FT232  | Wire Colour|
+|-------------|-------------|-----------|--------|------------|
+|   39 +3.3V  | 3.3V supply |    (VCC)  | VREF   |   Red      |
+|    1 GND    |     GND     |    (GND)  | GND    |   Black    |
+|    4 IO29   |     B19     |    (TDI)  | RXD    |   Green    |
+|    5 IO30   |     B12     |    (TMS)  | CTS    |   Blue     |
+|    6 IO31   |     B9      |    (TCK)  | TXD    |   White    |
+|    7 IO32   |     E6      |    (TDO)  | RTS    |   Yellow   |
 
 [[!img 2020-11-03_13-22.png size="900x" ]]