mention page number of vgbbd

[libreriscv.git] / HDL_workflow / ECP5_FPGA.mdwn

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
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--- a/HDL_workflow/ECP5_FPGA.mdwn
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@@ -1,11 +1,26 @@
 # ULX3S JTAG Connection with ft232r
 
+Note: this page is for connecting a *secondary* JTAG connection to
+the Libre-SOC Core, in order to test the actual HDL implementation
+of JTAG.  "Normal" JTAG documentation instructs you how to connect
+to the **FPGA** hard-macro JTAG port (in some fashion).  Whilst the
+FPGA has a JTAG port as a hard-macro these instructions do **not**
+apply to that: they apply **specifically** to actual implementation
+in HDL of a JTAG TAP interface suitable for deployment on an ASIC,
+and, consequently, in order to test that, four GPIO pads had to be
+picked to bring those signals out.  These instructions describe how
+to correctly wire up an FT232r to connect to those four GPIO pads.
+
 Cross referenced with:
 
 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
 
 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
 
+<https://www.amazon.co.uk/DSD-TECH-adapter-FT232RL-Compatible/dp/B07BBPX8B8/ref=sr_1_11?dchild=1&keywords=ft232&qid=1632498288&s=amazon-devices&sr=1-11>
+
+<https://www.amazon.co.uk/Elegoo-120pcs-Multicolored-Breadboard-arduino-colorful/dp/B01EV70C78/>
+
 ## Original Instructions
 
 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>