# ULX3S JTAG Connection with ft232r
+Note: this page is for connecting a *secondary* JTAG connection to
+the Libre-SOC Core, in order to test the actual HDL implementation
+of JTAG. "Normal" JTAG documentation instructs you how to connect
+to the **FPGA** hard-macro JTAG port (in some fashion). Whilst the
+FPGA has a JTAG port as a hard-macro these instructions do **not**
+apply to that: they apply **specifically** to actual implementation
+in HDL of a JTAG TAP interface suitable for deployment on an ASIC,
+and, consequently, in order to test that, four GPIO pads had to be
+picked to bring those signals out. These instructions describe how
+to correctly wire up an FT232r to connect to those four GPIO pads.
+
Cross referenced with:
<https://bugs.libre-soc.org/show_bug.cgi?id=517>
<http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
+<https://www.amazon.co.uk/DSD-TECH-adapter-FT232RL-Compatible/dp/B07BBPX8B8/ref=sr_1_11?dchild=1&keywords=ft232&qid=1632498288&s=amazon-devices&sr=1-11>
+
+<https://www.amazon.co.uk/Elegoo-120pcs-Multicolored-Breadboard-arduino-colorful/dp/B01EV70C78/>
+
## Original Instructions
See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
+``` from http://openocd.org/doc/html/Debug-Adapter-Configuration.html#index-ftdi
+List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
-``` ft232 pin and wire colour table converted to jtag signal names
- _________________________
-| Pin # | Name | Colour |
-|-------|------|----------|
-| 1 | GND | Black |
-| 2 | TMS | Brown |
-| 3 | VCC | Red |
-| 4 | TCK | Orange |
-| 5 | TDI | Yellow |
-| 6 | TDO | Green |
-|_______|______|__________|
+ - RXD(5) - TDI
+ - TXD(1) - TCK
+ - RTS(3) - TDO
+ - CTS(11) - TMS
+ - DTR(2) - TRST
+ - DCD(10) - SRST
```
+``` from https://github.com/ntfreak/openocd/blob/master/src/jtag/drivers/ft232r.c#L79-L99
+/**
+ * FT232R GPIO bit number to RS232 name
+ */
+#define FT232R_BIT_COUNT 8
+static char *ft232r_bit_name_array[FT232R_BIT_COUNT] = {
+ "TXD", /* 0: pin 1 TCK output */
+ "RXD", /* 1: pin 5 TDI output */
+ "RTS", /* 2: pin 3 TDO input */
+ "CTS", /* 3: pin 11 TMS output */
+ "DTR", /* 4: pin 2 /TRST output */
+ "DSR", /* 5: pin 9 unused */
+ "DCD", /* 6: pin 10 /SYSRST output */
+ "RI" /* 7: pin 6 unused */
+};
+
+static int tck_gpio; /* initialized to 0 by default */
+static int tdi_gpio = 1;
+static int tdo_gpio = 2;
+static int tms_gpio = 3;
+static int ntrst_gpio = 4;
+static int nsysrst_gpio = 6;
+```
+
+```from ft232 usb to 6 pin female header manual
+
+ft232 pin and wire colour table converted to jtag signal names:
+
+```
+|-------|------|--------|----------|
+| Pin # | JTAG | FT232 | Colour |
+|-------|------|--------|----------|
+| 1 | VCC | VCC | Red |
+| 2 | GND | GND | Black |
+| 3 | TCK | TXD | White |
+| 4 | TDI | RXD | Green |
+| 5 | TDO | RTS | Yellow |
+| 6 | TMS | CTS | Blue |
+|-------|------|--------|----------|
+```
Proposed FPGA External Pin to ft232r JTAG pin connections:
```
|2 | 3.3v | IO VOLT REF | IO VOLT REF | 3 (VCC) | Red |
|3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED | NOT |
|4 |-|(GND)| NONE | GND | 1 (GND) | Black |
-|5 (J1_5-) | 0 | C11 | gn[0] | 5 (TDI) | Yellow |
-|6 (J1_5+) | 0 | B11 | gp[0] | 2 (TMS) | Brown |
-|7 (J1_7-) | 1 | A11 | gn[1] | 4 (TCK) | Orange |
-|8 (J1_7+) | 1 | A10 | gp[1] | 6 (TDO) | Green |
+|5 (J1_5-) | 0 | C11 | gn[0] | 5 (TDI) | Green |
+|6 (J1_5+) | 0 | B11 | gp[0] | 2 (TMS) | Blue |
+|7 (J1_7-) | 1 | A11 | gn[1] | 4 (TCK) | White |
+|8 (J1_7+) | 1 | A10 | gp[1] | 6 (TDO) | Yellow |
|_____________|_______|_____________|_____________|________________|___________|
```
| |
|(3 VCC) red [VREF] 2 |3.3V| 1 NOT NOT NOT |
|(1 GND) black [GND] 4 | -| | 3 NOT NOT NOT |
-|(2 TMS) brown [GP0] 6 | 0 | 5 [GN0] yellow (5 TDI) |
-|(6 TDO) green [GP1] 8 | 1 | 7 [GN1] orange (4 TCK) |
+|(2 TMS) Blue [GP0] 6 | 0 | 5 [GN0] Green (5 TDI) |
+|(6 TDO) Yellow [GP1] 8 | 1 | 7 [GN1] White (4 TCK) |
|_________________________________________________________|
```
-## Images of wires on FPGA and on ft232r
+## Images of wires on ulx3s FPGA and on ft232r (lkcl to update images for Versa ECP5)
+
+Image of JTAG jumper wire connections on ULX3S FPGA side:
-Image of JTAG jumper wire connections on ULX3S FPGA side
+[[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]]
-[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]]
+Image of JTAG jumper wire connections on ft232r side:
-Image of JTAG jumper wire connections on ft232r side
+[[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]]
+
+Colour markings on ft232r side:
+
+[[!img HDL_workflow/ft232.png size="500x" ]]
# VERSA ECP5 Connections
Table of connections:
-| X3 pin # | FPGA IO PAD | ft232r |Wire Colour|
-|-------------|-------------|-----------|-----------|
-| 39 +3.3V | 3.3V supply | 3 (VCC) | Red |
-| 1 GND | GND | 1 (GND) | Black |
-| 4 IO29 | B19 | 5 (TDI) | Yellow |
-| 5 IO30 | B12 | 2 (TMS) | Brown |
-| 6 IO31 | B9 | 4 (TCK) | Orange |
-| 7 IO32 | E6 | 6 (TDO) | Green |
+| X3 pin # | FPGA IO PAD | Function | FT232 | Wire Colour|
+|-------------|-------------|-----------|--------|------------|
+| 39 +3.3V | 3.3V supply | (VCC) | VREF | Red |
+| 1 GND | GND | (GND) | GND | Black |
+| 4 IO29 | B19 | (TDI) | RXD | Green |
+| 5 IO30 | B12 | (TMS) | CTS | Blue |
+| 6 IO31 | B9 | (TCK) | TXD | White |
+| 7 IO32 | E6 | (TDO) | RTS | Yellow |
[[!img 2020-11-03_13-22.png size="900x" ]]
[[!img 2020-11-03_13-25.png size="900x" ]]
[[!img versa_ecp5_x3_connector.jpg size="900x" ]]
+
projects / libreriscv.git / blobdiff