# HyperRAM connections
+* jumper wires <https://www.amazon.co.uk/Elegoo-120pcs-Multicolored-Breadboard-arduino-colorful/dp/B01EV70C78/>
+* Note that cables have to be really short, they may need to
+ be constructed and soldered
+ <https://www.amazon.co.uk/HALJIA-2-54mm-Dupont-Jumper-Connectors/dp/B06WWB66WL/>
* nmigen [hyperram.py](https://git.libre-soc.org/?p=lambdasoc.git;a=blob;f=lambdasoc/periph/hyperram.py;hb=HEAD) module
+* Winbond Datasheet for Quad 1bitsqared PMOD:
+ <https://ftp.libre-soc.org/W956x8MBYA_64Mb_HyperBus_pSRAM_TFBGA24_datasheet_A01-005_20211208.pdf>
+* Winbond Verilog Model for W956A8MBY:
+ <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
+* [[shakti/m_class/HyperRAM]]
+* <https://github.com/icebreaker-fpga/icebreaker-pmod/tree/master/quadhyperram>
+* <https://hackaday.io/project/168594-feather-wing-pmod-adapter> <https://github.com/TomKeddie/prj-pmod-feather>
```
from nmigen.resources.memory import HyperRAMResources
attrs=IOStandard("LVCMOS33"))
self.platform.add_extension(hyperram_ios)
io = self.platform.request("hyperram")
+hyperram = HyperRAM(io=io, phy_kls=HyperRAMPHY,
+ latency=7) # Winbond W956D8MBYA
+ # latency=6 for Cypress S27KL0641DABHI020
```
## 1bitsquared HyperRAM PMOD
| 8 IO5 | E13 | (RSTN) | Grey |
| 9 IO6 | A14 | (CKN) | Brown |
| 10 IO7 | C14 | (RWDS) | White |
-| 11 IO8 | D14 | (DQ7) | Green |
-| 12 IO9 | E14 | (DQ0) | Blue |
-| 13 IO10 | D11 | (DQ6) | Green |
-| 14 IO11 | C11 | (DQ1) | Purple |
-| 15 IO12 | A9 | (DQ5) | Orange |
-| 16 IO13 | B10 | (DQ2) | Grey |
-| 17 IO14 | D12 | (DQ4) | Yellow |
-| 18 IO15 | E12 | (DQ3) | White |
+| 11 IO8 | D14 | (DQ7) | Blue |
+| 12 IO9 | E14 | (DQ0) | Green |
+| 13 IO10 | D11 | (DQ6) | Purple |
+| 14 IO11 | C11 | (DQ1) | Orange |
+| 15 IO12 | A9 | (DQ5) | Grey |
+| 16 IO13 | B10 | (DQ2) | Yellow |
+| 17 IO14 | D12 | (DQ4) | White |
+| 18 IO15 | E12 | (DQ3) | Brown |
| 19 GND | GND | (GND) | Black |
| 20 +3.3V | 3.3V supply | (VCC) | Red |
-[[!img HDL_workflow/versa_ecp5_x3_hyperram.png size="900x" ]]
+[[!img HDL_workflow/versa_ecp5_x4_hyperram.png size="900x" ]]
[[!img 2020-11-03_13-25.png size="900x" ]]
+# Digilent Arty a7-100t Connections
+See <https://digilent.com/reference/_media/reference/programmable-logic/arty/arty_rm.pdf>
+
+[[!img 2022-03-22_15-56.png size="900x" ]]