fosdem2024_bigint/Makefile: add upload target

[libreriscv.git] / HDL_workflow / HyperRAM.mdwn

diff --git a/HDL_workflow/HyperRAM.mdwn b/HDL_workflow/HyperRAM.mdwn
index 9e0670b3d7fb0c9bc118cffa08784e2c8aa00d38..b41f4548d3abf8cec45b9cd33302c2ec8d419516 100644 (file)
--- a/HDL_workflow/HyperRAM.mdwn
+++ b/HDL_workflow/HyperRAM.mdwn
@@ -9,6 +9,9 @@
   <https://ftp.libre-soc.org/W956x8MBYA_64Mb_HyperBus_pSRAM_TFBGA24_datasheet_A01-005_20211208.pdf>
 * Winbond Verilog Model for W956A8MBY:
   <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
+* [[shakti/m_class/HyperRAM]]
+* <https://github.com/icebreaker-fpga/icebreaker-pmod/tree/master/quadhyperram>
+* <https://hackaday.io/project/168594-feather-wing-pmod-adapter> <https://github.com/TomKeddie/prj-pmod-feather>
 
 ```
 from nmigen.resources.memory import HyperRAMResources