fosdem2024_bigint/Makefile: add upload target

[libreriscv.git] / HDL_workflow / HyperRAM.mdwn

diff --git a/HDL_workflow/HyperRAM.mdwn b/HDL_workflow/HyperRAM.mdwn
index f18bc289af9a2dcc31657c1cbfd0dabcef6d33fe..b41f4548d3abf8cec45b9cd33302c2ec8d419516 100644 (file)
--- a/HDL_workflow/HyperRAM.mdwn
+++ b/HDL_workflow/HyperRAM.mdwn
@@ -10,6 +10,8 @@
 * Winbond Verilog Model for W956A8MBY:
   <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
 * [[shakti/m_class/HyperRAM]]
+* <https://github.com/icebreaker-fpga/icebreaker-pmod/tree/master/quadhyperram>
+* <https://hackaday.io/project/168594-feather-wing-pmod-adapter> <https://github.com/TomKeddie/prj-pmod-feather>
 
 ```
 from nmigen.resources.memory import HyperRAMResources