# HyperRAM connections
+* jumper wires <https://www.amazon.co.uk/Elegoo-120pcs-Multicolored-Breadboard-arduino-colorful/dp/B01EV70C78/>
+* Note that cables have to be really short, they may need to
+ be constructed and soldered
+ <https://www.amazon.co.uk/HALJIA-2-54mm-Dupont-Jumper-Connectors/dp/B06WWB66WL/>
+* nmigen [hyperram.py](https://git.libre-soc.org/?p=lambdasoc.git;a=blob;f=lambdasoc/periph/hyperram.py;hb=HEAD) module
+* Winbond Datasheet for Quad 1bitsqared PMOD:
+ <https://ftp.libre-soc.org/W956x8MBYA_64Mb_HyperBus_pSRAM_TFBGA24_datasheet_A01-005_20211208.pdf>
+* Winbond Verilog Model for W956A8MBY:
+ <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
+* [[shakti/m_class/HyperRAM]]
+* <https://github.com/icebreaker-fpga/icebreaker-pmod/tree/master/quadhyperram>
+* <https://hackaday.io/project/168594-feather-wing-pmod-adapter> <https://github.com/TomKeddie/prj-pmod-feather>
+
+```
+from nmigen.resources.memory import HyperRAMResources
+hyperram_ios = HyperRAMResources(cs_n="B13 C13 A12 A13",
+ dq="E14 C11 B10 E12 D12 A9 D11 D14",
+ rwds="C14", rst_n="E13", clk_p="D13",
+ clk_n="A14", # only in DDR mode
+ attrs=IOStandard("LVCMOS33"))
+self.platform.add_extension(hyperram_ios)
+io = self.platform.request("hyperram")
+hyperram = HyperRAM(io=io, phy_kls=HyperRAMPHY,
+ latency=7) # Winbond W956D8MBYA
+ # latency=6 for Cypress S27KL0641DABHI020
+```
+
## 1bitsquared HyperRAM PMOD
* <https://1bitsquared.de/products/pmod-hyperram>
-| Pin | Function | Pin | Function |
-| --- | -------- | --- | -------- |
-| Top 7 | NC | Top 1 | NC |
-| Top 8 | DQ4 | Top 2 | DQ3 |
-| Top 9 | DQ2 | Top 3 | RWDS |
-| Top 10 | CSN | Top 4 | RESETN |
-| Top 11 | GND | Top 5 | GND |
-| Top 12 | 3V3 | Top 6 | 3V3 |
-
-| Pin | Function | Pin | Function |
-| --- | -------- | --- | -------- |
-| Bot 7 | CK | Bot 1 | CKN |
-| Bot 8 | DQ1 | Bot 2 | DQ7 |
-| Bot 9 | DQ6 | Bot 3 | DQ0 |
-| Bot 10 | DQ5 | Bot 4 | NC |
-| Bot 11 | GND | Bot 5 | GND |
-| Bot 12 | 3V3 | Bot 6 | 3V3 |
-
-[[!img HDL_workflow/ENtvxc9WwAAGyzl.png size="400x" ]]
-[[!img HDL_workflow/ENw4bZ8W4AM8FOS.png size="400x" ]]
-[[!img HDL_workflow/ENxOeloWsAMSw5u.jpeg size="400x" ]]
-
-[[!img HDL_workflow/pmod-hyperram-64mbit-dual-pmod_large.jpg size="500x" ]]
+| Pin | Function | Colour | Pin | Function | Colour |
+| --- | -------- | ---------| --- | -------- | ---------|
+| Top 7 | CS3N | Blue | Top 1 | CS2N | Green |
+| Top 8 | CS1N | Purple | Top 2 | CS0N | Orange |
+| Top 9 | RESETN | Grey | Top 3 | CK | Yellow |
+| Top 10 | RWDS | White | Top 4 | CKN | Brown |
+| Top 11 | GND | Black | Top 5 | GND | Black |
+| Top 12 | 3V3 | Red | Top 6 | 3V3 | Red |
+
+| Pin | Function | Colour | Pin | Function | Colour |
+| --- | -------- | ---------| --- | -------- | ---------|
+| Bot 7 | DQ7 | Blue | Bot 1 | DQ0 | Green |
+| Bot 8 | DQ6 | Purple | Bot 2 | DQ1 | Orange |
+| Bot 9 | DQ5 | Grey | Bot 3 | DQ2 | Yellow |
+| Bot 10 | DQ4 | White | Bot 4 | DQ3 | Brown |
+| Bot 11 | GND | Black | Bot 5 | GND | Black |
+| Bot 12 | 3V3 | Red | Bot 6 | 3V3 | Red |
+
+[[!img HDL_workflow/ENtvxc9WwAAGyzl.png size="400x" ]]
+[[!img HDL_workflow/ENxOeloWsAMSw5u.jpeg size="500x" ]]
+
+[[!img HDL_workflow/ENw4bZ8W4AM8FOS.png size="900x" ]]
+
+[[!img HDL_workflow/pmod-hyperram-64mbit-dual-pmod_large.jpg size="700x" ]]
+
+[[!img HDL_workflow/hyperram_connected_pmod.jpg size="700x" ]]
# VERSA ECP5 Connections
Table of connections:
-| X3 pin # | FPGA IO PAD | Function | Wire Colour|
+| X4 pin # | FPGA IO PAD | Function | Wire Colour|
|-------------|-------------|-----------|------------|
-| 8 IO33 | D6 | (DQ4) | Brown |
-| 9 IO34 | E7 | (DQ3) | Brown |
-| 10 IO35 | D7 | (DQ2) | Brown |
-| 11 IO36 | B11 | (RWDS) | Green |
-| 12 IO37 | B6 | (CSN) | Blue |
-| 13 IO38 | E9 | (RSTN) | Yellow |
-| 14 IO39 | B8 | (DQ5) | Green |
-| 15 IO40 | B8 | (DQ0) | Orange |
-| 16 IO41 | C8 | (DQ6) | Green |
-| 17 IO42 | D8 | (DQ7) | Orange |
-| 18 IO43 | E8 | (DQ1) | Green |
-| 19 IO44 | C7 | (CKN) | Purple |
-| 20 IO45 | C6 | (CK) | Yellow |
-| 25 +3.3V | 3.3V supply | (VCC) | Red |
-| 26 GND | GND | (GND) | Black |
-| 27 +3.3V | 3.3V supply | (VCC) | Red |
-| 28 GND | GND | (GND) | Black |
-| 35 +3.3V | 3.3V supply | (VCC) | Red |
-| 36 GND | GND | (GND) | Black |
-| 37 +3.3V | 3.3V supply | (VCC) | Red |
-| 38 GND | GND | (GND) | Black |
-
-[[!img versa_ecp5_x3_hyperram.png size="900x" ]]
-
-[[!img 2020-11-03_13-25.png size="900x" ]]
+| 3 IO0 | A12 | (CS2N) | Green |
+| 4 IO1 | A13 | (CS3N) | Blue |
+| 5 IO2 | B13 | (CS0N) | Orange |
+| 6 IO3 | C13 | (CS1N) | Purple |
+| 7 IO4 | D13 | (CK) | Yellow |
+| 8 IO5 | E13 | (RSTN) | Grey |
+| 9 IO6 | A14 | (CKN) | Brown |
+| 10 IO7 | C14 | (RWDS) | White |
+| 11 IO8 | D14 | (DQ7) | Blue |
+| 12 IO9 | E14 | (DQ0) | Green |
+| 13 IO10 | D11 | (DQ6) | Purple |
+| 14 IO11 | C11 | (DQ1) | Orange |
+| 15 IO12 | A9 | (DQ5) | Grey |
+| 16 IO13 | B10 | (DQ2) | Yellow |
+| 17 IO14 | D12 | (DQ4) | White |
+| 18 IO15 | E12 | (DQ3) | Brown |
+| 19 GND | GND | (GND) | Black |
+| 20 +3.3V | 3.3V supply | (VCC) | Red |
+
+[[!img HDL_workflow/versa_ecp5_x4_hyperram.png size="900x" ]]
+
+[[!img 2020-11-03_13-25.png size="900x" ]]
+
+# Digilent Arty a7-100t Connections
+See <https://digilent.com/reference/_media/reference/programmable-logic/arty/arty_rm.pdf>
+[[!img 2022-03-22_15-56.png size="900x" ]]
projects / libreriscv.git / blobdiff