(no commit message)

[libreriscv.git] / HDL_workflow / fpga.mdwn

diff --git a/HDL_workflow/fpga.mdwn b/HDL_workflow/fpga.mdwn
index 47ffe9aa1583b184eee82c3bbe2d1092520289f0..5ff231436a67d59d523e9c9f1785b89457b1327b 100644 (file)
--- a/HDL_workflow/fpga.mdwn
+++ b/HDL_workflow/fpga.mdwn
@@ -54,7 +54,11 @@ lkcl:
 
 ## Connecting the dots:
 
-litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
+Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
+
+STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
+
+Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 
     ("gpio", 0,
         Subsignal"p", Pins("B11")),
@@ -151,7 +155,7 @@ and therefore have no value are marked with 'NOT'
 
 ## Images of wires on FPGA and on STLINKV2
 
-pic fpga                                     pic stlinkv2
+[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="400x" ]]                                    
 
 ## Questions