fosdem2024_bigint: improve sv.adde diagram

[libreriscv.git] / HDL_workflow / gen_core_with_svp64.mdwn

diff --git a/HDL_workflow/gen_core_with_svp64.mdwn b/HDL_workflow/gen_core_with_svp64.mdwn
index 36579cf43be5507c43d3e1e51ec3b228fe365da0..888e6f891c8fc6add07efa2fd22fc61fe3f70df1 100644 (file)
--- a/HDL_workflow/gen_core_with_svp64.mdwn
+++ b/HDL_workflow/gen_core_with_svp64.mdwn
@@ -65,7 +65,7 @@ see [Bug #1127 comment #0](https://bugs.libre-soc.org/show_bug.cgi?id=1127#c0)
     (gen_cores):$ make pywriter
     (gen_cores):$ make pyfnwriter
     (gen_cores):$ cd ../soc/
-    (gen_cores):$ make microwatt_external_core
+    (gen_cores):$ make microwatt_external_core_svp64
 
 At this point you should end up with `external_core_top.v` verilog file, which
 contains the Libre-SOC core (with Microwatt-compatible interfaces).