got dia files to work, they're autoconverted to tex

[libreriscv.git] / HDL_workflow / litex_ls180.mdwn

diff --git a/HDL_workflow/litex_ls180.mdwn b/HDL_workflow/litex_ls180.mdwn
index 39e3c55776b6f84f308c0442b30e5b4b43aa20f8..b9553c4271b6ac8abafe2157cb94c9273c3f612c 100644 (file)
--- a/HDL_workflow/litex_ls180.mdwn
+++ b/HDL_workflow/litex_ls180.mdwn
@@ -1,5 +1,8 @@
 # Commits for litex:
 
+See <https://bugs.libre-soc.org/show_bug.cgi?id=700> for more
+specific commits of litex sub-packages
+
 the following have been identified as working with sim.py.  dependencies:
 
     litex commit 35929c0f8a8f1cc098a6b6ebb569caca8df8c08d 
@@ -35,4 +38,33 @@ into soclayout experiments9:
 and you can then begin the build process inside the coriolis2 chroot:
 
     cd soclayout/experiments9
-    nohup ./build_ls180.sh &
+    nohup ./build_full.sh &
+
+**note that you will need yosys checkout 049e3abf9 for the coriolis2 build**
+this is encoded into the dev-env-setup script which automates the chroot
+creation <https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis2-chroot;hb=HEAD>
+
+# build process for ls180 with 4k srams
+
+for the variant with 4k srams:
+
+    cd soc
+    make ls180_4k_verilog
+    cd src/soc/litex/florent
+    make ls1804k
+    cp ls180.il /tmp
+
+at this point you can copy ls180.il over to the coriolis2 chroot,
+into soclayout experiments9 in a **different** location from the
+above:
+
+    soclayout/experiments9/non_generated/full_core_4_4ksram_ls180.il 
+
+and you can then begin the build process inside the coriolis2 chroot:
+
+    cd soclayout/experiments9
+    nohup ./build_full_4ksram.sh &
+
+**note that you will need yosys checkout 049e3abf9 for the coriolis2 build**
+this is encoded into the dev-env-setup script which automates the chroot
+creation <https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis2-chroot;hb=HEAD>