(no commit message)

[libreriscv.git] / HDL_workflow / ls2.mdwn

diff --git a/HDL_workflow/ls2.mdwn b/HDL_workflow/ls2.mdwn
index 0eab0f0cc06d0cf1be7cade6c0334f0b8f75ad1c..3d8521dc7eef15452e8c339cc44c75fe235a2f8d 100644 (file)
--- a/HDL_workflow/ls2.mdwn
+++ b/HDL_workflow/ls2.mdwn
@@ -2,6 +2,7 @@
 
 * Currently works for Arty A7-100t, VERSA_ECP5 and in future others
 * Bugzilla page <https://bugs.libre-soc.org/show_bug.cgi?id=802>
+* NGI POINTER  <https://bugs.libre-soc.org/show_bug.cgi?id=818>
 
 # Install Instructions
 
@@ -56,6 +57,11 @@ If needed modify sources to produce a fixed file bitstream and
     minicom -D /dev/ttyUSB1
     xc3sprog -c nexys4 top.bit
 
+If there are multiple Arty-A7-100t boards connected you need to know
+the serial number (lsusb | grep Serial)
+
+    xc3sprog -c nexys4 -s {insert_full_serial_number} top.bit
+
 # Using ls2 with microwatt
 
 This is doable but tricky.  An older version is required at present.
@@ -91,7 +97,28 @@ The output of that command is:
     fw at address ff000000
     SRAM 0x8000 at address 0x0
 
+To use verilator, make sure to run the devscript:
+
+    ./verilator-install
+
+And set the GHDLSYNTH and update PATH:
+
+    export PATH=/usr/local/verilator/bin:$PATH
+    export GHDLSYNTH=ghdl
+
 After that you can compile microwatt-verilator:
 
        export FPGA_TARGET=verilator
        make microwatt-verilator
+
+# Estimating transistor count using yosys
+
+Use yosys to run synthesis and using `stat` to view gate/transistor count:
+
+    cd src/ls2/
+    yosys
+    yosys> read_verilog ls2.v external_core_top.v ../uart16550/rtl/verilog/*.v
+    yosys> synth
+    yosys> tee -a stat_cmos.log stat -tech cmos
+
+Then you can view the resulting log file afterwards. Bare in mind `synth` will probably take a while. **TODO: Find multi-threaded option**