* Currently works for Arty A7-100t, VERSA_ECP5 and in future others
* Bugzilla page <https://bugs.libre-soc.org/show_bug.cgi?id=802>
* NGI POINTER <https://bugs.libre-soc.org/show_bug.cgi?id=818>
+* [Bug #1127 - Generating core with SVP64](https://bugs.libre-soc.org/show_bug.cgi?id=1127)
# Install Instructions
./hdl-dev-repos
./hdl-tools-yosys
./nextpnr-xilinx-install
- export PATH=/usr/local/nextpnr-xilinx/bin:$PATH
- export XRAY_DIR=/usr/local/nextpnr-xilinx
./hdl-dev-ls2
+
+ # if you intend to upload fpga bitstreams in the same chroot, also need
+ # the fpga utilities
+ ./fpga-boot-load-prog-install
+
cd ~/src
# make hello_world.bin from microwatt
cd ../ls2
git checkout 426e2d9585cd4b1fb96a38987f97878285ee5ba7
+ export PATH=/usr/local/nextpnr-xilinx/bin:$PATH
+ export XRAY_DIR=/usr/local/nextpnr-xilinx
+
# plug in FPGA board (Arty A7-100t, VERSA_ECP5, other)
# run in 2nd terminal "minicom -D /dev/ttyUSB1"
export FPGA_TARGET=verilator
make microwatt-verilator
+
+# Estimating transistor count using yosys
+
+Use yosys to run synthesis and using `stat` to view gate/transistor count:
+
+ cd src/ls2/
+ yosys
+ yosys> read_verilog ls2.v external_core_top.v ../uart16550/rtl/verilog/*.v
+ yosys> synth
+ yosys> tee -a stat_cmos.log stat -tech cmos
+
+Then you can view the resulting log file afterwards. Bare in mind `synth` will probably take a while. **TODO: Find multi-threaded option**