sync_up: Discussion page for tomorrow's meeting

[libreriscv.git] / HDL_workflow / ls2.mdwn

diff --git a/HDL_workflow/ls2.mdwn b/HDL_workflow/ls2.mdwn
index edcd3eb9b1cc85460b055c915e745bae11e110de..da65c0cf90f7c7fb6e920b7c6f05bf4a2989df79 100644 (file)
--- a/HDL_workflow/ls2.mdwn
+++ b/HDL_workflow/ls2.mdwn
@@ -3,6 +3,7 @@
 * Currently works for Arty A7-100t, VERSA_ECP5 and in future others
 * Bugzilla page <https://bugs.libre-soc.org/show_bug.cgi?id=802>
 * NGI POINTER  <https://bugs.libre-soc.org/show_bug.cgi?id=818>
+* [Bug #1127 - Generating core with SVP64](https://bugs.libre-soc.org/show_bug.cgi?id=1127)
 
 # Install Instructions
 
@@ -23,9 +24,12 @@
     ./hdl-dev-repos
     ./hdl-tools-yosys
     ./nextpnr-xilinx-install
-    export PATH=/usr/local/nextpnr-xilinx/bin:$PATH
-    export XRAY_DIR=/usr/local/nextpnr-xilinx
     ./hdl-dev-ls2
+
+    # if you intend to upload fpga bitstreams in the same chroot, also need
+    # the fpga utilities
+    ./fpga-boot-load-prog-install
+
     cd ~/src
 
     # make hello_world.bin from microwatt
@@ -44,6 +48,9 @@
     cd ../ls2
     git checkout 426e2d9585cd4b1fb96a38987f97878285ee5ba7
 
+    export PATH=/usr/local/nextpnr-xilinx/bin:$PATH
+    export XRAY_DIR=/usr/local/nextpnr-xilinx
+
     # plug in FPGA board (Arty A7-100t, VERSA_ECP5, other)
     # run in 2nd terminal "minicom -D /dev/ttyUSB1"
 
@@ -57,6 +64,11 @@ If needed modify sources to produce a fixed file bitstream and
     minicom -D /dev/ttyUSB1
     xc3sprog -c nexys4 top.bit
 
+If there are multiple Arty-A7-100t boards connected you need to know
+the serial number (lsusb | grep Serial)
+
+    xc3sprog -c nexys4 -s {insert_full_serial_number} top.bit
+
 # Using ls2 with microwatt
 
 This is doable but tricky.  An older version is required at present.
@@ -92,7 +104,28 @@ The output of that command is:
     fw at address ff000000
     SRAM 0x8000 at address 0x0
 
+To use verilator, make sure to run the devscript:
+
+    ./verilator-install
+
+And set the GHDLSYNTH and update PATH:
+
+    export PATH=/usr/local/verilator/bin:$PATH
+    export GHDLSYNTH=ghdl
+
 After that you can compile microwatt-verilator:
 
        export FPGA_TARGET=verilator
        make microwatt-verilator
+
+# Estimating transistor count using yosys
+
+Use yosys to run synthesis and using `stat` to view gate/transistor count:
+
+    cd src/ls2/
+    yosys
+    yosys> read_verilog ls2.v external_core_top.v ../uart16550/rtl/verilog/*.v
+    yosys> synth
+    yosys> tee -a stat_cmos.log stat -tech cmos
+
+Then you can view the resulting log file afterwards. Bare in mind `synth` will probably take a while. **TODO: Find multi-threaded option**