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[libreriscv.git] / HDL_workflow / ls2.mdwn

diff --git a/HDL_workflow/ls2.mdwn b/HDL_workflow/ls2.mdwn
index 68e61ccf0f18c3396b2a0277bbbfc6e69f8394bf..edcd3eb9b1cc85460b055c915e745bae11e110de 100644 (file)
--- a/HDL_workflow/ls2.mdwn
+++ b/HDL_workflow/ls2.mdwn
@@ -2,6 +2,7 @@
 
 * Currently works for Arty A7-100t, VERSA_ECP5 and in future others
 * Bugzilla page <https://bugs.libre-soc.org/show_bug.cgi?id=802>
+* NGI POINTER  <https://bugs.libre-soc.org/show_bug.cgi?id=818>
 
 # Install Instructions
 
@@ -56,3 +57,42 @@ If needed modify sources to produce a fixed file bitstream and
     minicom -D /dev/ttyUSB1
     xc3sprog -c nexys4 top.bit
 
+# Using ls2 with microwatt
+
+This is doable but tricky.  An older version is required at present.
+
+    git clone https://git.libre-soc.org/git/microwatt.git
+    git checkout microwatt_verilator
+    make microwatt.v
+
+From there, some hand-editing is required.  search for core_NNNNNNN_XXX_YYY
+and rename it to external_core_top. Save the file as external_core_top.v
+and it can be used in place of the Libre-SOC Core, above.
+
+In fact any core can be used with ls, as long as it is compliant with
+the interfaces.  Both Wishbone Interfaces must be WB4 Pipeline
+compliant (proper stall handling) or the stall signal faked externally
+with a wrapper: `stall=stb&~ack`
+
+# Using ls2 with verilator
+
+first you need to build hello_world (or any other firmware) to start at 
+0xff000000. Then you can run build ls.v using that firmware:
+
+    python3 src/ls2.py sim /tmp/ff000000_hw.bin
+
+The output of that command is:
+
+    platform sim /tmp/ff000000_hw.bin None
+    fpga sim firmware /tmp/ff000000_hw.bin
+    ddr pins None
+    spiflash pins None
+    ethmac pins None
+    hyperram pins [<lambdasoc.periph.hyperram.HyperRAMPads object at 0x735e9940dd30>]
+    fw at address ff000000
+    SRAM 0x8000 at address 0x0
+
+After that you can compile microwatt-verilator:
+
+       export FPGA_TARGET=verilator
+       make microwatt-verilator