microwatt_tutorial: Fix formatting

[libreriscv.git] / HDL_workflow / microwatt_tutorial.mdwn

diff --git a/HDL_workflow/microwatt_tutorial.mdwn b/HDL_workflow/microwatt_tutorial.mdwn
index ddfbfd95563611b1c95c1097c99aa077afd697cb..03cb94bcde245aaa296cba19e6544698c60294b2 100644 (file)
--- a/HDL_workflow/microwatt_tutorial.mdwn
+++ b/HDL_workflow/microwatt_tutorial.mdwn
@@ -2,7 +2,7 @@
 
 useful links:
 
-* [Original Microwatt Libre-SOC wiki](microwatt)
+* Original Microwatt Libre-SOC page: [[microwatt]]
 * [Libre-SOC Microwatt repo branch](https://git.libre-soc.org/?p=microwatt.git;a=tree;hb=refs/heads/verilator_trace)
 * [Libre-SOC devscripts repo](https://git.libre-soc.org/?p=dev-env-setup.git;a=tree)
 
@@ -27,8 +27,9 @@ Make sure verilator binaries in $PATH:
 
 (GHDLSYNTH needs to be redefined because the Makefile has default `ghdl.so`,
 but somewhere else '.so' gets appended. You may see the following error if you
-don't redefine: `ERROR: Can't load module `./ghdl.so':
-/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`)
+don't redefine:
+`ERROR: Can't load module
+./ghdl.so':/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`)
 
 To run the Verilator simulation, set verilator as the target: