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[libreriscv.git] / HDL_workflow.mdwn

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index b972d1847edde7cc3823264e2b11179bdcff31b5..0c325e016e7af3e61a3c43e79a5770e0d088c911 100644 (file)
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -47,6 +47,8 @@ Whilst many resources online advocate "sudo" in front of all root-level commands
 * apt-get install graphviz xdot gtkwave
 * return to user prompt (ctrl-d)
 
+This will get you python3 and other tools that are needed. graphviz is essential fir showing the interconnections between cells, and gtkwave is essential for debugging.
+
 ## yosys
 
 Follow the source code (git clone) instructions here: <http://www.clifford.at/yosys/download.html>
@@ -148,6 +150,5 @@ The reasons for doing a proper modularisation job are several-fold:
 Find appropriate tutorials for nmigen and yosys, as well as symbiyosys.
 
 * Although a verilog example this is very useful to do <https://symbiyosys.readthedocs.io/en/latest/quickstart.html#first-step-a-simple-bmc-example>
-* There exist several nmigen examples which are also executable <https://github.com/m-labs/nmigen/tree/master/examples/>
 * This tutorial looks pretty good and will get you started <http://blog.lambdaconcept.com/doku.php?id=nmigen:nmigen_install> and walks not just through simulation, it takes you through using gtkwave as well.
-
+* There exist several nmigen examples which are also executable <https://github.com/m-labs/nmigen/tree/master/examples/> exactly as described in the above tutorial (python3 filename.py -h)