(no commit message)

[libreriscv.git] / HDL_workflow.mdwn

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index c82b9e32b077a9aaeb80422f2840498af16113c0..45a0cb13ce86972c7d081281b1b86a35a101c0d1 100644 (file)
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -340,11 +340,15 @@ and that people communicate and coordinate with each other.
 This is not a hard rule: under special cirmstances branches can be useful.
 They should not however be considered "routine".
 
+For advice on commit messages see
+[here](https://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html),
+and [here](https://github.com/torvalds/subsurface-for-dirk/blob/master/README.md#contributing)).
+
 ## yosys
 
 Follow the source code (git clone) instructions here, do **not** use
 the "stable" version (do not download the tarball):
-<http://www.clifford.at/yosys/download.html>
+<https://github.com/YosysHQ/yosys>
 
 Or, alternatively, use the
 [hdl-tools-yosys](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-tools-yosys;hb=HEAD)
@@ -353,7 +357,7 @@ script (which also installs symbiyosys and its dependencies)
 Do not try to use a fixed revision of yosys (currently 0.9), nmigen is
 evolving and frequently interacts with yosys.
 
-[Yosys](http://www.clifford.at/yosys/) is a framework for Verilog RTL.
+[Yosys](https://github.com/YosysHQ/yosys is a framework for Verilog RTL.
 [Verilog](https://en.wikipedia.org/wiki/Verilog) is a hardware description
 language.
 RTL [Register Transfer
@@ -927,6 +931,11 @@ the double import of the class from two separate locations, immediately.
 
 Really.  don't.  use.  wildcards.
 
+More about this here:
+
+* <https://www.asmeurer.com/removestar/>
+* <https://rules.sonarsource.com/python/RSPEC-2208>
+
 ### Keep file and variables short but clear
 
 * try to keep both filenames and variable names short but not ridiculously