correct indention

[libreriscv.git] / HDL_workflow.mdwn

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index b87847b6ecc43449254083dfd8adba4823634e2e..4a4221714feb42776a27f0e8341a65b5e4e2aee4 100644 (file)
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -344,7 +344,7 @@ They should not however be considered "routine".
 
 Follow the source code (git clone) instructions here, do **not** use
 the "stable" version (do not download the tarball):
-<http://www.clifford.at/yosys/download.html>
+<https://github.com/YosysHQ/yosys>
 
 Or, alternatively, use the
 [hdl-tools-yosys](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-tools-yosys;hb=HEAD)
@@ -353,7 +353,7 @@ script (which also installs symbiyosys and its dependencies)
 Do not try to use a fixed revision of yosys (currently 0.9), nmigen is
 evolving and frequently interacts with yosys.
 
-[Yosys](http://www.clifford.at/yosys/) is a framework for Verilog RTL.
+[Yosys](https://github.com/YosysHQ/yosys is a framework for Verilog RTL.
 [Verilog](https://en.wikipedia.org/wiki/Verilog) is a hardware description
 language.
 RTL [Register Transfer
@@ -439,7 +439,7 @@ In the meantime, sfpy can be built as follows:
 You can test your installation by doing the following:
 
     python3
-    >>> from sfpy import *
+    >>> from sfpy import Posit8
     >>> Posit8(1.3)
 
 It should print out `Posit8(1.3125)`
@@ -581,10 +581,12 @@ See [[HDL_workflow/cocotb]] page for installation instructions.
 
 ## Symbiflow
 
-needed for the Arty A7 100t Digilent FPGA board
+A fully open source toolchain for the development of FPGAs. Currently it targets Xilinx 7-series, Lattice iCE40 and ECP5, Quicklogic EOS S3.
+
+Needed for the Arty A7 100t Digilent FPGA board.
 
 See [[HDL_workflow/symbiflow]] for installation instructions
-and dependencies
+and dependencies.
 
 # Registering for git repository access<a name="gitolite3_access"></a>