(no commit message)

[libreriscv.git] / HDL_workflow.mdwn

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index 1a3b699c04e49da9c41328ad3bdd57303365ff97..79b959b3a5cee1b41edc3d61f0a98d81c9ea4a18 100644 (file)
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -24,10 +24,12 @@ Therefore, we need not only to be "self-sufficient" (absolutely under no circums
 The main message here: **use the right tool for the right job**.
 
 * mailing list: general communication and discussion.
+* irc channel #libre-soc: real(ish)-time communication.
 * bugtracker: task-orientated, goal-orientated *focussed* discussion.
 * ikiwiki: document store, information store, and (editable) main website
 * git repositories: code stores (**not binary or auto-generated output store**)
-* ftp server (<https://ftp.libre-soc.org/>): large file store.
+* ftp server (<https://ftp.libre-soc.org/>): large (temporary,
+  auto-generated) file store.
 
 we will add an IRC channel at some point when there are enough people
 to warrant having one (and it will be publicly archived)
@@ -395,7 +397,7 @@ Install gdb from source.  Obtain the latest tarball, unpack it, then:
      ../configure --srcdir=.. --host=x86_64-linux --target=powerpc64-linux-gnu
     make -j$(nproc)
     make install
-    
+
 ## power_instruction_analyzer (pia)
 
 We have a custom tool built in rust by programmerjake to help analyze
@@ -427,7 +429,17 @@ Note: an ongoing bug in maturin interferes with successful installation.  This c
 
 ## Coriolis2
 
-See [[coriolis2]] page, for those people doing layout work.
+See [[HDL_workflow/coriolis2]] page, for those people doing layout work.
+
+## Chips4Makers JTAG
+
+As this is an actual ASIC, we do not rely on an FPGA's JTAG TAP interface, instead require a full complete independent implementation of JTAG. Staf Verhaegen has one, with a full test suite, and it is superb and well-written.  The Libre-SOC version includes DMI (Debug Memory Interface):
+
+    git clone https://git.libre-soc.org/c4m-jtag.git
+
+Included is an IDCODE tap point, Wishbone Master (for direct memory read and write, fully independent of the core), IOPad redirection and testing, and general purpose shift register capability for any custom use.
+
+We added a DMI to JTAG bridge in LibreSOC which is directly connected to the core, to access registers and to be able to start and stop the core and change the PC.  In combination with the JTAG Wishbone interface the test ASIC can have a bootloader uploaded directly into onboard SRAM and execution begun.
 
 # Registering for git repository access
 
@@ -482,6 +494,7 @@ if you want it, always ensure that a new git checkout is set up with rebase.
 * cd !$
 * git clone gitolite3@git.libre-soc.org:nmutil.git
 * git clone gitolite3@git.libre-soc.org:ieee754fpu.git
+* git clone gitolite3@git.libre-soc.org:nmigen-soc.git
 * git clone gitolite3@git.libre-soc.org:soc.git
 
 In each of these directories, in the order listed, track down the