add AMX

[libreriscv.git] / HDL_workflow.mdwn

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index d65d6411cac07577208cdca1194b51f69bd7877d..94e9ed30ee9a6c1e27350487371b9ec5fd2f774d 100644 (file)
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -381,7 +381,9 @@ circumstances).
 front-end driver program for Yosys-based formal hardware verification
 flows.
 
-## nmigen
+## nmigen (TM)
+
+*nmigen is a registered trademark of M-Labs <https://uspto.report/TM/88980893>*
 
 **PLEASE NOTE: it is critical to install nmigen as the first dependency
 prior to installing any further python-based Libre-SOC HDL repositories.
@@ -551,6 +553,15 @@ See [[HDL_workflow/nextpnr]] page for installation instructions of nextpnr with
 [[HDL_workflow/ECP5_FPGA]] for connecting up to JTAG with a ULX3S
 and the Lattice VERSA_ECP5.
 
+## Nextpnr-xilinx
+
+An open source place and route framework for Xilinx FPGAs using Project Xray. We will use it for Xilinx 7-series FPGAs like Artix-7.
+
+One of the ways to get Arty A7 100t Digilent FPGA board working.
+
+See [[HDL_workflow/nextpnr-xilinx]] for installation instructions and dependencies.
+
+
 ## Verilator
 
 The fastest Verilog and SystemVerilog simulator. It compiles Verilog to C++ or SystemC.
@@ -587,18 +598,24 @@ See [[HDL_workflow/cocotb]] page for installation instructions.
 
 A fully open source toolchain for the development of FPGAs. Currently it targets Xilinx 7-series, Lattice iCE40 and ECP5, Quicklogic EOS S3.
 
-Needed for the Arty A7 100t Digilent FPGA board.
+One way to get the Arty A7 100t Digilent FPGA board working.
 
 See [[HDL_workflow/symbiflow]] for installation instructions
 and dependencies.
 
-## Nextpnr-xilinx
+## FPGA/Board Boot-Loaders-Programmers
 
-An open source place and route framework for Xilinx FPGAs using Project Xray. We will use it for Xilinx 7-series FPGAs like Artix-7.
+Open source FPGA/Board boot-loaders and programmers for ULX3S, ECP5 and
+OrangeCrab.
 
-Needed for Arty A7 100t Digilent FPGA board.
+Currently these programs dfu-util, openFPGALoader, ujprog, fujprog,
+xc3sprog and ecpprog are going to be used.
 
-See [[HDL_workflow/nextpnr-xilinx]] for installation instructions and dependencies.
+See [[HDL_workflow/fpga-boot-loaders-progs]] for installation instructions and dependencies.
+
+## ls2 peripheral fabric
+
+[[HDL_workflow/ls2]]
 
 # Registering for git repository access<a name="gitolite3_access"></a>
 
@@ -677,15 +694,17 @@ you of what it is doing**.
 
 * mkdir ~/src
 * cd !$
-* git clone gitolite3@git.libre-soc.org:nmigen.git
+* git clone https://gitlab.com/nmigen/nmigen
+* git clone https://gitlab.com/nmigen/nmigen-boards
+* git clone https://gitlab.com/nmigen/nmigen-soc
+* git clone https://gitlab.com/nmigen/nmigen-stdio
 * git clone gitolite3@git.libre-soc.org:c4m-jtag.git
 * git clone gitolite3@git.libre-soc.org:nmutil.git
 * git clone gitolite3@git.libre-soc.org:openpower-isa.git
 * git clone gitolite3@git.libre-soc.org:ieee754fpu.git
-* git clone gitolite3@git.libre-soc.org:nmigen-soc.git
 * git clone gitolite3@git.libre-soc.org:soc.git
 
-In each of these directories, **in the order listed***, track down the
+In each of these directories, **in the order listed**, track down the
 `setup.py` file, then, as root (`sudo bash`), run the following:
 
 * python3 setup.py develop
@@ -1090,6 +1109,42 @@ Simply mark it with an appropriate
 preferably with a link to a URL in the [bugtracker](https://bugs.libre-soc.org/)
 with further details as to why the unit test should not be run.
 
+# Task management guidelines
+
+1. Create the task in appropriate "Product" section with appropriate
+  "Component" section. Most code tasks generally use "Libre-SOC's
+  first SOC".
+2. Fill in "Depends on" and "Blocks" section whenever appropriate.
+   Also add as many related ("See Also") links to other bugreports
+   as possible. bugreports are never isolated.
+3. Choose the correct task for a budget allocation. Usually the parent
+  task is used.
+4. Choose the correct NLnet milestone. The best practice is to check
+  the parent task for a correct milestone.
+5. Assign the budget to the task in `"USER=SUM"` form, where "USER"
+  corresponds to your username and "SUM" corresponds to the actual
+  budget in EUR. There may be multiple users.
+6. When the task is completed, you can begin writing an RFP.
+   **DO NOT submit it without explicit authorisation and review**.
+   Leave out your bank and personal address details if you prefer
+   when sending to the Team Manager for review.
+7. Once the RFP is written, notify the Team Manager and obtain their
+   explicit approval to send it.
+8. Once approval is received and the RFP sent, update the `"USER=SUM"`
+  field to include the submitted date:
+  `"USER={amount=SUM, submitted=SDATE}"`. The SDATE is entered in
+  `YYYY-MM-DD` form.
+9. Once the task is paid, again notify the Team Manager (IRC is fine),
+  and update `"USER={amount=SUM, submitted=SDATE}"`
+  to `"USER={amount=SUM, submitted=SDATE, paid=PDATE}"`. The PDATE is
+  entered in `YYYY-MM-DD` form, too.
+
+Throughout all of this you should be using budget-sync to check the
+database consistency
+<https://git.libre-soc.org/?p=utils.git;a=blob;f=README.txt;hb=HEAD>
+
+[[!img bugzilla_RFP_fields.jpg size=640x ]]
+
 # TODO Tutorials
 
 Find appropriate tutorials for nmigen and yosys, as well as symbiyosys.