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[libreriscv.git] / HDL_workflow.mdwn

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index 21bc60f45fb53959d15d371e2d78613b393b5227..d65d6411cac07577208cdca1194b51f69bd7877d 100644 (file)
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -340,11 +340,15 @@ and that people communicate and coordinate with each other.
 This is not a hard rule: under special cirmstances branches can be useful.
 They should not however be considered "routine".
 
+For advice on commit messages see
+[here](https://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html),
+and [here](https://github.com/torvalds/subsurface-for-dirk/blob/master/README.md#contributing)).
+
 ## yosys
 
 Follow the source code (git clone) instructions here, do **not** use
 the "stable" version (do not download the tarball):
-<http://www.clifford.at/yosys/download.html>
+<https://github.com/YosysHQ/yosys>
 
 Or, alternatively, use the
 [hdl-tools-yosys](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-tools-yosys;hb=HEAD)
@@ -353,7 +357,7 @@ script (which also installs symbiyosys and its dependencies)
 Do not try to use a fixed revision of yosys (currently 0.9), nmigen is
 evolving and frequently interacts with yosys.
 
-[Yosys](http://www.clifford.at/yosys/) is a framework for Verilog RTL.
+[Yosys](https://github.com/YosysHQ/yosys is a framework for Verilog RTL.
 [Verilog](https://en.wikipedia.org/wiki/Verilog) is a hardware description
 language.
 RTL [Register Transfer
@@ -387,7 +391,7 @@ If "pip3 list" shows that nmigen has been auto-installed please remove it**
 
 * mkdir ~/src
 * cd !$
-* git clone https://github.com/nmigen/nmigen.git
+* git clone https://gitlab.com/nmigen/nmigen.git
 * cd nmigen
 * sudo bash
 * python3 setup.py develop
@@ -439,7 +443,7 @@ In the meantime, sfpy can be built as follows:
 You can test your installation by doing the following:
 
     python3
-    >>> from sfpy import *
+    >>> from sfpy import Posit8
     >>> Posit8(1.3)
 
 It should print out `Posit8(1.3125)`
@@ -588,6 +592,14 @@ Needed for the Arty A7 100t Digilent FPGA board.
 See [[HDL_workflow/symbiflow]] for installation instructions
 and dependencies.
 
+## Nextpnr-xilinx
+
+An open source place and route framework for Xilinx FPGAs using Project Xray. We will use it for Xilinx 7-series FPGAs like Artix-7.
+
+Needed for Arty A7 100t Digilent FPGA board.
+
+See [[HDL_workflow/nextpnr-xilinx]] for installation instructions and dependencies.
+
 # Registering for git repository access<a name="gitolite3_access"></a>
 
 After going through the onboarding process and having agreed to take
@@ -927,6 +939,11 @@ the double import of the class from two separate locations, immediately.
 
 Really.  don't.  use.  wildcards.
 
+More about this here:
+
+* <https://www.asmeurer.com/removestar/>
+* <https://rules.sonarsource.com/python/RSPEC-2208>
+
 ### Keep file and variables short but clear
 
 * try to keep both filenames and variable names short but not ridiculously
@@ -1086,6 +1103,6 @@ Find appropriate tutorials for nmigen and yosys, as well as symbiyosys.
   and walks not just through simulation, it takes you through using
   gtkwave as well.
 * There exist several nmigen examples which are also executable
-  <https://github.com/nmigen/nmigen/tree/master/examples/> exactly as
+  <https://gitlab.com/nmigen/nmigen/tree/master/examples/> exactly as
   described in the above tutorial (python3 filename.py -h)
 * More nmigen tutorials at [[learning_nmigen]]