(no commit message)

[libreriscv.git] / HDL_workflow.mdwn

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index 3bb13ee9454eaf31f6f16eac92aa81e6fcfdf90d..de49bfa61c2691d56afb12479a038677085a4f65 100644 (file)
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -24,10 +24,12 @@ Therefore, we need not only to be "self-sufficient" (absolutely under no circums
 The main message here: **use the right tool for the right job**.
 
 * mailing list: general communication and discussion.
+* irc channel #libre-soc: real(ish)-time communication.
 * bugtracker: task-orientated, goal-orientated *focussed* discussion.
 * ikiwiki: document store, information store, and (editable) main website
 * git repositories: code stores (**not binary or auto-generated output store**)
-* ftp server (<https://ftp.libre-soc.org/>): large file store.
+* ftp server (<https://ftp.libre-soc.org/>): large (temporary,
+  auto-generated) file store.
 
 we will add an IRC channel at some point when there are enough people
 to warrant having one (and it will be publicly archived)
@@ -42,7 +44,7 @@ To respect the transparency requirements, conversations need to be
 public and archived (i.e not skype, not telegram, not discord,
 and anyone seriously suggesting slack will be thrown to the
 lions).  Therefore we have a mailing list. Everything goes through
-there. <https://lists.libre-soc.org/mailman/listinfo/libre-riscv-dev>
+there. <https://lists.libre-soc.org/mailman/listinfo/libre-soc-dev>
 therefore please do google "mailing list etiquette" and at the very
 minimum look up and understand the following:
 
@@ -76,7 +78,7 @@ minimum look up and understand the following:
 
 If discussions result in any actionable items, it is important not to
 lose track of them. Create a bugreport, find the discussion in the
-archives <https://lists.libre-soc.org/pipermail/libre-riscv-dev/>,
+archives <https://lists.libre-soc.org/pipermail/libre-soc-dev/>,
 and put the link actually in the bugtracker as one of the comments.
 
 At some point in any discussion, the sudden realisation may dawn on one
@@ -429,9 +431,15 @@ Note: an ongoing bug in maturin interferes with successful installation.  This c
 
 See [[HDL_workflow/coriolis2]] page, for those people doing layout work.
 
-## Coriolis2
+## Chips4Makers JTAG
+
+As this is an actual ASIC, we do not rely on an FPGA's JTAG TAP interface, instead require a full complete independent implementation of JTAG. Staf Verhaegen has one, with a full test suite, and it is superb and well-written.  The Libre-SOC version includes DMI (Debug Memory Interface):
+
+    git clone https://git.libre-soc.org/c4m-jtag.git
+
+Included is an IDCODE tap point, Wishbone Master (for direct memory read and write, fully independent of the core), IOPad redirection and testing, and general purpose shift register capability for any custom use.
 
-See [[HDL_workflow/blahblah]] page, for those people doing layout work.
+We added a DMI to JTAG bridge in LibreSOC which is directly connected to the core, to access registers and to be able to start and stop the core and change the PC.  In combination with the JTAG Wishbone interface the test ASIC can have a bootloader uploaded directly into onboard SRAM and execution begun.
 
 # Registering for git repository access