get arty a7-100t functional

[libresoc-litex.git] / Makefile

diff --git a/Makefile b/Makefile
index 1bfeeb3e7747128f2886a762cad0a3d11ac29109..18916edcccdf0a7976ff25b59091b4440ac2dd6a 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -42,3 +42,7 @@ versaecp5:
 
 versaecp5load:
        ./versa_ecp5.py --sys-clk-freq=55e6 --load
+
+artya7100t:
+       python3 ./versa_ecp5.py --sys-clk-freq=100e6 --build  --fpga=artya7100t \
+                    --toolchain=symbiflow