GHDL ?= ghdl
-GHDLFLAGS=--std=08 --work=unisim
+GHDLFLAGS=--std=08 -frelaxed
CFLAGS=-O3 -Wall
GHDLSYNTH ?= ghdl.so
all: $(all)
core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
- fetch2.vhdl utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
+ utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
decode1.vhdl helpers.vhdl insn_helpers.vhdl gpr_hazard.vhdl \
cr_hazard.vhdl control.vhdl decode2.vhdl register_file.vhdl \
cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
core.vhdl
-soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl \
- wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl
+soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
+ wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
+ spi_rxtx.vhdl spi_flash_ctrl.vhdl
-soc_sim_files = sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \
- sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl \
- sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl \
- sim-unisim/unisim_vcomponents.vhdl dmi_dtm_xilinx.vhdl
+uart_files = $(wildcard uart16550/*.v)
+
+soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
+ sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
+ sim_16550_uart.vhdl
soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
sim_jtag_socket_c.c
+
soc_sim_obj_files=$(soc_sim_c_files:.c=.o)
comma := ,
soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
+unisim_dir = sim-unisim
+unisim_lib = $(unisim_dir)/unisim-obj08.cf
+unisim_lib_files = $(unisim_dir)/BSCANE2.vhdl $(unisim_dir)/BUFG.vhdl \
+ $(unisim_dir)/unisim_vcomponents.vhdl
+$(unisim_lib): $(unisim_lib_files)
+ $(GHDL) -i --std=08 --work=unisim --workdir=$(unisim_dir) $^
+GHDLFLAGS += -P$(unisim_dir)
+
core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
-soc_dram_tbs = core_dram_tb
+soc_flash_tbs = core_flash_tb
+soc_dram_tbs = dram_tb core_dram_tb
+
+ifneq ($(FLASH_MODEL_PATH),)
+fmf_dir = $(FLASH_MODEL_PATH)/fmf
+fmf_lib = $(fmf_dir)/fmf-obj08.cf
+fmf_lib_files = $(wildcard $(fmf_dir)/*.vhd)
+GHDLFLAGS += -P$(fmf_dir)
+$(fmf_lib): $(fmf_lib_files)
+ $(GHDL) -i --std=08 --work=fmf --workdir=$(fmf_dir) $^
+
+flash_model_files=$(FLASH_MODEL_PATH)/s25fl128s.vhd
+flash_model_files: $(fmf_lib)
+else
+flash_model_files=sim_no_flash.vhdl
+fmf_lib=
+endif
-$(soc_tbs): %: $(core_files) $(soc_files) $(soc_sim_files) $(soc_sim_obj_files) %.vhdl
- $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(core_files) $(soc_files) $(soc_sim_files) $@.vhdl -e $@
+$(soc_flash_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) $(fmf_lib) $(flash_model_files) %.vhdl
+ $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $(flash_model_files) $@.vhdl $(unisim_files) -e $@
+
+$(soc_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) %.vhdl
+ $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $@.vhdl -e $@
$(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
$(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
$(CC) $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
-soc_dram_files = $(soc_files) litedram/extras/wrapper-mw-init.vhdl litedram/generated/sim/litedram-initmem.vhdl
+soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files)
-$(soc_dram_tbs): %: $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) %.vhdl
- $(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $@.vhdl -e $@
+$(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) $(flash_model_files) $(unisim_lib) $(fmf_lib) %.vhdl
+ $(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(soc_dram_files) $(soc_dram_sim_files) $(flash_model_files) $@.vhdl -e $@
endif
# Hello world
#MEMORY_SIZE=393216
#RAM_INIT_FILE=micropython/firmware.hex
+FPGA_TARGET ?= ORANGE-CRAB
+
# OrangeCrab with ECP85
+ifeq ($(FPGA_TARGET), ORANGE-CRAB)
RESET_LOW=true
CLK_INPUT=50000000
-CLK_FREQUENCY=50000000
+CLK_FREQUENCY=40000000
LPF=constraints/orange-crab.lpf
PACKAGE=CSFBGA285
-NEXTPNR_FLAGS=--um5g-85k --freq 50
+NEXTPNR_FLAGS=--um5g-85k --freq 40
OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
+endif
# ECP5-EVN
-#RESET_LOW=true
-#CLK_INPUT=12000000
-#CLK_FREQUENCY=12000000
-#LPF=constraints/ecp5-evn.lpf
-#PACKAGE=CABGA381
-#NEXTPNR_FLAGS=--um5g-85k --freq 12
-#OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
-#OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
+ifeq ($(FPGA_TARGET), ECP5-EVN)
+RESET_LOW=true
+CLK_INPUT=12000000
+CLK_FREQUENCY=40000000
+LPF=constraints/ecp5-evn.lpf
+PACKAGE=CABGA381
+NEXTPNR_FLAGS=--um5g-85k --freq 40
+OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
+OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
+endif
GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
-clkgen=fpga/clk_gen_bypass.vhd
+clkgen=fpga/clk_gen_ecp5.vhd
toplevel=fpga/top-generic.vhdl
dmi_dtm=dmi_dtm_dummy.vhdl
synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
-microwatt.json: $(synth_files)
- $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@"
+microwatt.json: $(synth_files) $(RAM_INIT_FILE)
+ $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files)
-microwatt.v: $(synth_files)
- $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
+microwatt.v: $(synth_files) $(RAM_INIT_FILE)
+ $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" $(uart_files)
# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
@cp -f obj_dir/microwatt-verilator microwatt-verilator
microwatt_out.config: microwatt.json $(LPF)
- $(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
+ $(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@.tmp $(NEXTPNR_FLAGS) --package $(PACKAGE)
+ mv -f $@.tmp $@
microwatt.bit: microwatt_out.config
$(ECPPACK) --svf microwatt.svf $< $@
tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
-check: $(tests) $(tests_console) test_micropython test_micropython_long
+tests_console: $(tests_console)
-check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long $(tests_console)
+check: $(tests) tests_console test_micropython test_micropython_long tests_unit
+
+check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
$(tests): core_tb
@./scripts/run_test.sh $@
test_micropython_long: core_tb
@./scripts/test_micropython_long.py
+tests_core_tb = $(patsubst %_tb,%_tb_test,$(core_tbs))
+tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs))
+
+%_test: %
+ ./$< --assert-level=error > /dev/null
+
+tests_core: $(tests_core_tb)
+
+tests_soc: $(tests_soc_tb)
+
+# FIXME SOC tests have bit rotted, so disable for now
+#tests_unit: tests_core tests_soc
+tests_unit: tests_core
+
TAGS:
find . -name '*.vhdl' | xargs ./scripts/vhdltags
.PHONY: TAGS
_clean:
- rm -f *.o work-*cf unisim-*cf $(all)
- rm -f fpga/*.o fpga/work-*cf
- rm -f sim-unisim/*.o sim-unisim/unisim-*cf
+ rm -f *.o *.cf $(all)
+ rm -f fpga/*.o fpga/*.cf
+ rm -f sim-unisim/*.o sim-unisim/*.cf
rm -f litedram/extras/*.o
rm -f TAGS
rm -f scripts/mw_debug/*.o
projects / microwatt.git / blobdiff