--enable-xics --enable-sram4x4kblock --disable-svp64 \
src/soc/litex/florent/libresoc/libresoc.v
-# build microwatt "external core"
+# build microwatt "external core", note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
microwatt_external_core:
- python3 simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+ external_core_top.v
+
+# build microwatt "external core" with fixed 64-bit width SVP64
+# note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
+microwatt_external_core_svp64:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat-svp64 --enable-mmu \
+ external_core_top.v
+
+microwatt_external_core_spi:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+ --small-cache \
+ --enable-mmu \
+ --pc-reset 0x10000000 \
+ external_core_top.v
+
+# microwatt-compatible core with smaller cache size (quick. VERSA_ECP5. just)
+microwatt_external_core_bram:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+ --small-cache \
+ --enable-mmu \
+ --pc-reset 0xFF000000 \
+ external_core_top.v
+
+# microwatt-compatible core with larger cache size (experiment on arty)
+microwatt_external_core_bram_arty:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+ --enable-mmu \
+ --pc-reset 0xFF000000 \
external_core_top.v
# build the litex libresoc SoC without 4k SRAMs