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divide shiftrot pipeline into 2 (simple last)
[soc.git]
/
Makefile
diff --git
a/Makefile
b/Makefile
index 1df83c53d67950fc38b6145aded81d7aba02c61b..2228b2c6559b3a5fb21e6e5d9e32da3595675c3f 100644
(file)
--- a/
Makefile
+++ b/
Makefile
@@
-11,7
+11,7
@@
install:
python3 src/soc/decoder/pseudo/pywriter.py
run_sim: install
- # TODO: get it to work
+ python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/libresoc.v
python3 src/soc/litex/florent/sim.py --cpu=libresoc
test: install