Add Tercel PHY reset synchronization

[microwatt.git] / Makefile

diff --git a/Makefile b/Makefile
index 9349d8379836e02b5a96b041b62afec84c259bac..d8db01ffe6547324b0c0c0b817bcb28b97a4a70c 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 GHDL ?= ghdl
 GHDLFLAGS=--std=08
 CFLAGS=-O3 -Wall
-VERILATOR_FLAGS=-O3
+VERILATOR_FLAGS=-O3 #--trace
 # It takes forever to build with optimisation, so disable by default
 #VERILATOR_CFLAGS=-O3
 
@@ -119,7 +119,7 @@ $(soc_dram_tbs):
 else
 
 verilated_dram: litedram/generated/sim/litedram_core.v
-       verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
+       verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $<
        make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
 
 SIM_DRAM_CFLAGS  = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
@@ -171,11 +171,44 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif
 
+# Arctic Tern with ECP85
+ifeq ($(FPGA_TARGET), ARCTIC-TERN)
+RESET_LOW=true
+CLK_INPUT=125000000
+CLK_FREQUENCY=48000000
+LPF=constraints/arctic-tern.lpf
+PACKAGE=CABGA381
+NEXTPNR_FLAGS=--um5g-85k --freq 48 --ignore-loops
+OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
+OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
+toplevel=fpga/top-rcs-arctic-tern-bmc-card.vhdl
+soc_files   += litedram/extras/litedram-wrapper-l2.vhdl \
+       litedram/generated/rcs-arctic-tern-bmc-card/litedram-initmem.vhdl
+soc_extra_v += litedram/generated/rcs-arctic-tern-bmc-card/litedram_core.v
+soc_extra_v += liteeth/generated/rcs-arctic-tern-bmc-card/liteeth_core.v
+soc_extra_v += pinyon/wishbone_interface.v
+soc_extra_v += tercel/phy.v
+soc_extra_v += tercel/wishbone_spi_master.v
+soc_extra_v += aquila/io_blocks.v
+soc_extra_v += aquila/lpc_slave.v
+soc_extra_v += aquila/wishbone_lpc_slave_interface.v
+soc_extra_v += aquila/third_party/async_fifo/async_bidir_fifo.v
+soc_extra_v += aquila/third_party/async_fifo/async_bidir_ramif_fifo.v
+soc_extra_v += aquila/third_party/async_fifo/async_fifo.v
+soc_extra_v += aquila/third_party/async_fifo/fifo_2mem.v
+soc_extra_v += aquila/third_party/async_fifo/fifomem_dp.v
+soc_extra_v += aquila/third_party/async_fifo/rptr_empty.v
+soc_extra_v += aquila/third_party/async_fifo/sync_ptr.v
+soc_extra_v += aquila/third_party/async_fifo/sync_r2w.v
+soc_extra_v += aquila/third_party/async_fifo/sync_w2r.v
+soc_extra_v += aquila/third_party/async_fifo/wptr_full.v
+endif
+
 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
        -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
 
 clkgen=fpga/clk_gen_ecp5.vhd
-toplevel=fpga/top-generic.vhdl
+toplevel ?= fpga/top-generic.vhdl
 dmi_dtm=dmi_dtm_dummy.vhdl
 
 ifeq ($(FPGA_TARGET), verilator)
@@ -192,14 +225,14 @@ fpga_files = fpga/soc_reset.vhdl \
 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
-       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
+       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
 
 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
-       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
+       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
-       verilator $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc $< --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
+       verilator $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc $< --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT
        make -C obj_dir -f Vmicrowatt.mk
        @cp -f obj_dir/microwatt-verilator microwatt-verilator