Add Tercel PHY reset synchronization

[microwatt.git] / Makefile

diff --git a/Makefile b/Makefile
index e2783a2af80c5699404ae3232c31ee5adf0e997b..d8db01ffe6547324b0c0c0b817bcb28b97a4a70c 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -171,11 +171,44 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif
 
+# Arctic Tern with ECP85
+ifeq ($(FPGA_TARGET), ARCTIC-TERN)
+RESET_LOW=true
+CLK_INPUT=125000000
+CLK_FREQUENCY=48000000
+LPF=constraints/arctic-tern.lpf
+PACKAGE=CABGA381
+NEXTPNR_FLAGS=--um5g-85k --freq 48 --ignore-loops
+OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
+OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
+toplevel=fpga/top-rcs-arctic-tern-bmc-card.vhdl
+soc_files   += litedram/extras/litedram-wrapper-l2.vhdl \
+       litedram/generated/rcs-arctic-tern-bmc-card/litedram-initmem.vhdl
+soc_extra_v += litedram/generated/rcs-arctic-tern-bmc-card/litedram_core.v
+soc_extra_v += liteeth/generated/rcs-arctic-tern-bmc-card/liteeth_core.v
+soc_extra_v += pinyon/wishbone_interface.v
+soc_extra_v += tercel/phy.v
+soc_extra_v += tercel/wishbone_spi_master.v
+soc_extra_v += aquila/io_blocks.v
+soc_extra_v += aquila/lpc_slave.v
+soc_extra_v += aquila/wishbone_lpc_slave_interface.v
+soc_extra_v += aquila/third_party/async_fifo/async_bidir_fifo.v
+soc_extra_v += aquila/third_party/async_fifo/async_bidir_ramif_fifo.v
+soc_extra_v += aquila/third_party/async_fifo/async_fifo.v
+soc_extra_v += aquila/third_party/async_fifo/fifo_2mem.v
+soc_extra_v += aquila/third_party/async_fifo/fifomem_dp.v
+soc_extra_v += aquila/third_party/async_fifo/rptr_empty.v
+soc_extra_v += aquila/third_party/async_fifo/sync_ptr.v
+soc_extra_v += aquila/third_party/async_fifo/sync_r2w.v
+soc_extra_v += aquila/third_party/async_fifo/sync_w2r.v
+soc_extra_v += aquila/third_party/async_fifo/wptr_full.v
+endif
+
 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
        -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
 
 clkgen=fpga/clk_gen_ecp5.vhd
-toplevel=fpga/top-generic.vhdl
+toplevel ?= fpga/top-generic.vhdl
 dmi_dtm=dmi_dtm_dummy.vhdl
 
 ifeq ($(FPGA_TARGET), verilator)