xilinx: add delays to INV

[yosys.git] / Makefile

diff --git a/Makefile b/Makefile
index 374d42f6f832c1b299812d532935a7f536cc073b..e9dfd9df07be9d197725ba8126116249faaafa74 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -128,7 +128,7 @@ bumpversion:
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 144c5be
+ABCREV = 71f2b40
 ABCPULL = 1
 ABCURL ?= https://github.com/berkeley-abc/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
@@ -728,6 +728,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
        +cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT)
        +cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
        +cd tests/rpc && bash run-test.sh
+       +cd tests/memfile && bash run-test.sh
        @echo ""
        @echo "  Passed \"make test\"."
        @echo ""