that have ports with a width that depends on a parameter.
- The ``hdlname`` attribute is used by some passes to document the original
- (HDL) name of a module when renaming a module.
+ (HDL) name of a module when renaming a module. It should contain a single
+ name, or, when describing a hierarchical name in a flattened design, multiple
+ names separated by a single space character.
- The ``keep`` attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that
- enums are supported (including inside packages)
- but are currently not strongly typed
-- structs are supported
+- packed structs and unions are supported.
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.