graphviz xdot pkg-config python3 libboost-system-dev \
libboost-python-dev libboost-filesystem-dev zlib1g-dev
-Similarily, on Mac OS X Homebrew can be used to install dependencies:
+Similarily, on Mac OS X Homebrew can be used to install dependencies (from within cloned yosys repository):
$ brew tap Homebrew/bundle && brew bundle
- The ``clkbuf_sink`` attribute can be set on an input port of a module to
request clock buffer insertion by the ``clkbufmap`` pass.
+- The ``clkbuf_inv`` attribute can be set on an output port of a module
+ with the value set to the name of an input port of that module. When
+ the ``clkbufmap`` would otherwise insert a clock buffer on this output,
+ it will instead try inserting the clock buffer on the input port (this
+ is used to implement clock inverter cells that clock buffer insertion
+ will "see through").
+
- The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent
automatic clock buffer insertion by ``clkbufmap``. This behaviour can be
overridden by providing a custom selection to ``clkbufmap``.
+- The ``invertible_pin`` attribute can be set on a port to mark it as
+ invertible via a cell parameter. The name of the inversion parameter
+ is specified as the value of this attribute. The value of the inversion
+ parameter must be of the same width as the port, with 1 indicating
+ an inverted bit and 0 indicating a non-inverted bit.
+
- The ``iopad_external_pin`` attribute on a blackbox module's port marks
it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
from inserting another pad cell on it.
-- The module attribute ``abc_box_id`` specifies a positive integer linking a
- blackbox or whitebox definition to a corresponding entry in a `abc9`
- box-file.
+- The module attribute ``abc9_lut`` is an integer attribute indicating to
+ `abc9` that this module describes a LUT with an area cost of this value, and
+ propagation delays described using `specify` statements.
+
+- The module attribute ``abc9_box`` is a boolean specifying a black/white-box
+ definition, with propagation delays described using `specify` statements, for
+ use by `abc9`.
-- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
+- The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
carry-out (if output port) ports of a box. This information is necessary for
`abc9` to preserve the integrity of carry-chains. Specifying this attribute
onto a bus port will affect only its most significant bit.
-- The port attribute ``abc_arrival`` specifies an integer (for output ports
- only) to be used as the arrival time of this sequential port. It can be used,
- for example, to specify the clk-to-Q delay of a flip-flop for consideration
- during techmapping.
+- The module attribute ``abc9_flop`` is a boolean marking the module as a
+ flip-flop. This allows `abc9` to analyse its contents in order to perform
+ sequential synthesis.
+
+- The frontend sets attributes ``always_comb``, ``always_latch`` and
+ ``always_ff`` on processes derived from SystemVerilog style always blocks
+ according to the type of the always. These are checked for correctness in
+ ``proc_dlatch``.
+
+- The cell attribute ``wildcard_port_conns`` represents wildcard port
+ connections (SystemVerilog ``.*``). These are resolved to concrete
+ connections to matching wires in ``hierarchy``.
- In addition to the ``(* ... *)`` attribute syntax, Yosys supports
the non-standard ``{* ... *}`` attribute syntax to set default attributes
...
endmodule
+- The ``wiretype`` attribute is added by the verilog parser for wires of a
+ typedef'd type to indicate the type identifier.
+
+- Various ``enum_{width}_{value}`` attributes are added to wires of an
+ enumerated type to give a map of possible enum items to their values.
+
+- The ``enum_base_type`` attribute is added to enum items to indicate which
+ enum they belong to (enums -- anonymous and otherwise -- are
+ automatically named with an auto-incrementing counter). Note that enums
+ are currently not strongly typed.
+
- A limited subset of DPI-C functions is supported. The plugin mechanism
(see ``help plugin``) can be used to load .so files with implementations
of DPI-C routines. As a non-standard extension it is possible to specify
expressions over parameters and constant values are allowed). The intended
use for this is synthesis-time DRC.
-- There is limited support for converting specify .. endspecify statements to
- special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in
- blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
- functionality. (By default specify .. endspecify blocks are ignored.)
+- There is limited support for converting ``specify`` .. ``endspecify``
+ statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells,
+ for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
+ enable this functionality. (By default these blocks are ignored.)
Non-standard or SystemVerilog features for formal verification
into a design with ``read_verilog``, all its packages are available to
SystemVerilog files being read into the same design afterwards.
+- typedefs are supported (including inside packages)
+ - type identifiers must currently be enclosed in (parentheses) when declaring
+ signals of that type (this is syntactically incorrect SystemVerilog)
+ - type casts are currently not supported
+
+- enums are supported (including inside packages)
+ - but are currently not strongly typed
+
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.