xilinx: consider DSP48E1.ADREG

[yosys.git] / README.md

diff --git a/README.md b/README.md
index e4301e7bf9ecabbe4f47b69402b8857fff72d67b..79801d23f9f83916b2a05d06fd546a143136892f 100644 (file)
--- a/README.md
+++ b/README.md
@@ -69,7 +69,7 @@ prerequisites for building yosys:
                graphviz xdot pkg-config python3 libboost-system-dev \
                libboost-python-dev libboost-filesystem-dev zlib1g-dev
 
-Similarily, on Mac OS X Homebrew can be used to install dependencies:
+Similarily, on Mac OS X Homebrew can be used to install dependencies (from within cloned yosys repository):
 
        $ brew tap Homebrew/bundle && brew bundle
 
@@ -364,25 +364,19 @@ Verilog Attributes and non-standard features
   it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
   from inserting another pad cell on it.
 
-- The module attribute ``abc9_box_id`` specifies a positive integer linking a
-  blackbox or whitebox definition to a corresponding entry in a `abc9`
-  box-file.
+- The module attribute ``abc9_lut`` is an integer attribute indicating to
+  `abc9` that this module describes a LUT with an area cost of this value, and
+  propagation delays described using `specify` statements.
+
+- The module attribute ``abc9_box`` is a boolean specifying a black/white-box
+  definition, with propagation delays described using `specify` statements, for
+  use by `abc9`.
 
 - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
   carry-out (if output port) ports of a box. This information is necessary for
   `abc9` to preserve the integrity of carry-chains. Specifying this attribute
   onto a bus port will affect only its most significant bit.
 
-- The output port attribute ``abc9_arrival`` specifies an integer, or a string
-  of space-separated integers to be used as the arrival time of this blackbox
-  port. It can be used, for example, to specify the clk-to-Q delay of a flip-
-  flop output for consideration during `abc9` techmapping.
-
-- The input port attribute ``abc9_required`` specifies an integer, or a string
-  of space-separated integers to be used as the required time of this blackbox
-  port. It can be used, for example, to specify the setup-time of a flip-flop
-  input for consideration during `abc9` techmapping.
-
 - The module attribute ``abc9_flop`` is a boolean marking the module as a
   flip-flop. This allows `abc9` to analyse its contents in order to perform
   sequential synthesis.
@@ -446,6 +440,17 @@ Verilog Attributes and non-standard features
         ...
       endmodule
 
+- The ``wiretype`` attribute is added by the verilog parser for wires of a
+  typedef'd type to indicate the type identifier.
+
+- Various ``enum_{width}_{value}`` attributes are added to wires of an
+  enumerated type to give a map of possible enum items to their values.
+
+- The ``enum_base_type`` attribute is added to enum items to indicate which
+  enum they belong to (enums -- anonymous and otherwise -- are
+  automatically named with an auto-incrementing counter). Note that enums
+  are currently not strongly typed.
+
 - A limited subset of DPI-C functions is supported. The plugin mechanism
   (see ``help plugin``) can be used to load .so files with implementations
   of DPI-C routines. As a non-standard extension it is possible to specify
@@ -536,6 +541,12 @@ from SystemVerilog:
   SystemVerilog files being read into the same design afterwards.
 
 - typedefs are supported (including inside packages)
+       - type identifiers must currently be enclosed in (parentheses) when declaring
+         signals of that type (this is syntactically incorrect SystemVerilog)
+       - type casts are currently not supported
+
+- enums are supported (including inside packages)
+       - but are currently not strongly typed
 
 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
   ports are inputs or outputs are supported.