Fix handling of (* keep *) wires in wreduce

[yosys.git] / README.md

diff --git a/README.md b/README.md
index 0fba1cb461c3e73134d1ab26ed5bce946c3052c9..840f2c8b25515f9ea4fd72bf8be3b216fd12c2dd 100644 (file)
--- a/README.md
+++ b/README.md
@@ -452,6 +452,9 @@ from SystemVerilog:
   into a design with ``read_verilog``, all its packages are available to
   SystemVerilog files being read into the same design afterwards.
 
+- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
+  ports are inputs or outputs are supported.
+
 
 Building the documentation
 ==========================