Add tests/various/chparam.sh

[yosys.git] / README.md

diff --git a/README.md b/README.md
index fd45b54704f877f8b36146b39b7624123580ddfe..913777f2ee463933d82573fc6de33aed488e8447 100644 (file)
--- a/README.md
+++ b/README.md
@@ -66,25 +66,26 @@ prerequisites for building yosys:
 
        $ sudo apt-get install build-essential clang bison flex \
                libreadline-dev gawk tcl-dev libffi-dev git \
-               graphviz xdot pkg-config python3
+               graphviz xdot pkg-config python3 libboost-system-dev \
+               libboost-python-dev libboost-filesystem-dev
 
 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
 
        $ brew tap Homebrew/bundle && brew bundle
        $ sudo port install bison flex readline gawk libffi \
-               git graphviz pkgconfig python36
+               git graphviz pkgconfig python36 boost
 
 On FreeBSD use the following command to install all prerequisites:
 
        # pkg install bison flex readline gawk libffi\
-               git graphviz pkgconfig python3 python36 tcl-wrapper
+               git graphviz pkgconfig python3 python36 tcl-wrapper boost-libs
 
 On FreeBSD system use gmake instead of make. To run tests use:
     % MAKE=gmake CC=cc gmake test
 
 For Cygwin use the following command to install all prerequisites, or select these additional packages:
 
-       setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel
+       setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build
 
 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
 as a source distribution for Visual Studio. Visit the Yosys download page for
@@ -369,7 +370,7 @@ Verilog Attributes and non-standard features
 
 - When defining a macro with `define, all text between triple double quotes
   is interpreted as macro body, even if it contains unescaped newlines. The
-  tipple double quotes are removed from the macro body. For example:
+  triple double quotes are removed from the macro body. For example:
 
       `define MY_MACRO(a, b) """
          assign a = 23;
@@ -456,7 +457,7 @@ Non-standard or SystemVerilog features for formal verification
   supported in any clocked block.
 
 - The syntax ``@($global_clock)`` can be used to create FFs that have no
-  explicit clock input ($ff cells). The same can be achieved by using
+  explicit clock input (``$ff`` cells). The same can be achieved by using
   ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
   is marked with the ``(* gclk *)`` Verilog attribute.
 
@@ -469,7 +470,7 @@ from SystemVerilog:
 
 - The ``assert`` statement from SystemVerilog is supported in its most basic
   form. In module context: ``assert property (<expression>);`` and within an
-  always block: ``assert(<expression>);``. It is transformed to a $assert cell.
+  always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
 
 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
   also supported. The same limitations as with the ``assert`` statement apply.