Add to CHANGELOG

[yosys.git] / README.md

diff --git a/README.md b/README.md
index 195329a372b7fbede2bab1eec0e1cdf021e9177f..94ea9538ff4bd05bf6b40f2e0140db307fe7bfec 100644 (file)
--- a/README.md
+++ b/README.md
@@ -257,7 +257,7 @@ for them:
 - Non-synthesizable language features as defined in
        IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
 
-- The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
+- The ``tri``, ``triand`` and ``trior`` net types
 
 - The ``config`` and ``disable`` keywords and library map files
 
@@ -413,12 +413,13 @@ Verilog Attributes and non-standard features
       $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
 
 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
-  expressions as <size>. If the expression is not a simple identifier, it
+  expressions as ``<size>``. If the expression is not a simple identifier, it
   must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
 
-- The system tasks ``$finish`` and ``$display`` are supported in initial blocks
-  in an unconditional context (only if/case statements on parameters
-  and constant values). The intended use for this is synthesis-time DRC.
+- The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in
+  initial blocks in an unconditional context (only if/case statements on
+  expressions over parameters and constant values are allowed). The intended
+  use for this is synthesis-time DRC.
 
 - There is limited support for converting specify .. endspecify statements to
   special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in