```
yosys -- Yosys Open SYnthesis Suite
-Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com>
+Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com>
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
============================
More information and documentation can be found on the Yosys web site:
-- http://www.clifford.at/yosys/
+- https://yosyshq.net/yosys/
The "Documentation" page on the web site contains links to more resources,
including a manual that even describes some of the Yosys internals:
-- http://www.clifford.at/yosys/documentation.html
+- https://yosyshq.net/yosys/documentation.html
-The file `CodingReadme` in this directory contains additional information
+The directory `guidelines` contains additional information
for people interested in using the Yosys C++ APIs.
Users interested in formal verification might want to use the formal verification
There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
as a source distribution for Visual Studio. Visit the Yosys download page for
-more information: http://www.clifford.at/yosys/download.html
+more information: https://yosyshq.net/yosys/download.html
To configure the build system to use a specific compiler, use one of
that have ports with a width that depends on a parameter.
- The ``hdlname`` attribute is used by some passes to document the original
- (HDL) name of a module when renaming a module.
+ (HDL) name of a module when renaming a module. It should contain a single
+ name, or, when describing a hierarchical name in a flattened design, multiple
+ names separated by a single space character.
- The ``keep`` attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that
for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
enable this functionality. (By default these blocks are ignored.)
+- The ``reprocess_after`` internal attribute is used by the Verilog frontend to
+ mark cells with bindings which might depend on the specified instantiated
+ module. Modules with such cells will be reprocessed during the ``hierarchy``
+ pass once the referenced module definition(s) become available.
+
Non-standard or SystemVerilog features for formal verification
==============================================================
==========================
Note that there is no need to build the manual if you just want to read it.
-Simply download the PDF from http://www.clifford.at/yosys/documentation.html
+Simply download the PDF from https://yosyshq.net/yosys/documentation.html
instead.
On Ubuntu, texlive needs these packages to be able to build the manual: