```
yosys -- Yosys Open SYnthesis Suite
-Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com>
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
============================
More information and documentation can be found on the Yosys web site:
-- http://www.clifford.at/yosys/
+- https://yosyshq.net/yosys/
The "Documentation" page on the web site contains links to more resources,
including a manual that even describes some of the Yosys internals:
-- http://www.clifford.at/yosys/documentation.html
+- https://yosyshq.net/yosys/documentation.html
-The file `CodingReadme` in this directory contains additional information
+The directory `guidelines` contains additional information
for people interested in using the Yosys C++ APIs.
Users interested in formal verification might want to use the formal verification
There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
as a source distribution for Visual Studio. Visit the Yosys download page for
-more information: http://www.clifford.at/yosys/download.html
+more information: https://yosyshq.net/yosys/download.html
To configure the build system to use a specific compiler, use one of
$ make test
+To use a separate (out-of-tree) build directory, provide a path to the Makefile.
+
+ $ mkdir build; cd build
+ $ make -f ../Makefile
+
+Out-of-tree builds require a clean source tree.
+
Getting Started
===============
temporary variable within an always block. This is mostly used internally
by Yosys to synthesize Verilog functions and access arrays.
+- The ``nowrshmsk`` attribute on a register prohibits the generation of
+ shift-and-mask type circuits for writing to bit slices of that register.
+
- The ``onehot`` attribute on wires mark them as one-hot state register. This
is used for example for memory port sharing and set by the fsm_map pass.
that have ports with a width that depends on a parameter.
- The ``hdlname`` attribute is used by some passes to document the original
- (HDL) name of a module when renaming a module.
+ (HDL) name of a module when renaming a module. It should contain a single
+ name, or, when describing a hierarchical name in a flattened design, multiple
+ names separated by a single space character.
- The ``keep`` attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that
- The cell attribute ``wildcard_port_conns`` represents wildcard port
connections (SystemVerilog ``.*``). These are resolved to concrete
- connections to matching wires in ``hierarchy``.
+ connections to matching wires in ``hierarchy``.
- In addition to the ``(* ... *)`` attribute syntax, Yosys supports
the non-standard ``{* ... *}`` attribute syntax to set default attributes
- The ``wiretype`` attribute is added by the verilog parser for wires of a
typedef'd type to indicate the type identifier.
-- Various ``enum_{width}_{value}`` attributes are added to wires of an
- enumerated type to give a map of possible enum items to their values.
+- Various ``enum_value_{value}`` attributes are added to wires of an enumerated type
+ to give a map of possible enum items to their values.
- The ``enum_base_type`` attribute is added to enum items to indicate which
enum they belong to (enums -- anonymous and otherwise -- are
for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
enable this functionality. (By default these blocks are ignored.)
+- The ``reprocess_after`` internal attribute is used by the Verilog frontend to
+ mark cells with bindings which might depend on the specified instantiated
+ module. Modules with such cells will be reprocessed during the ``hierarchy``
+ pass once the referenced module definition(s) become available.
+
Non-standard or SystemVerilog features for formal verification
==============================================================
SystemVerilog files being read into the same design afterwards.
- typedefs are supported (including inside packages)
- - type identifiers must currently be enclosed in (parentheses) when declaring
- signals of that type (this is syntactically incorrect SystemVerilog)
- type casts are currently not supported
- enums are supported (including inside packages)
- but are currently not strongly typed
+- packed structs and unions are supported.
+
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.
==========================
Note that there is no need to build the manual if you just want to read it.
-Simply download the PDF from http://www.clifford.at/yosys/documentation.html
+Simply download the PDF from https://yosyshq.net/yosys/documentation.html
instead.
On Ubuntu, texlive needs these packages to be able to build the manual:
projects / yosys.git / blobdiff