get arty a7-100t functional

[libresoc-litex.git] / README.txt

diff --git a/README.txt b/README.txt
index 3d008ebf7092cfa3d0f73115338064932c0df034..b7eb1414fe9951a5cb62fff6e67f5225248fd4a4 100644 (file)
--- a/README.txt
+++ b/README.txt
@@ -13,3 +13,10 @@ same thing: first build libresoc.v and copy it to the libresoc/ directory
 
 ./versa_ecp5.py --sys-clk-freq=55e6 --build --yosys-nowidelut
 ./versa_ecp5.py --sys-clk-freq=55e6 --load
+
+# arty a7 build
+
+export PATH=$PATH:/usr/local/symbiflow/bin/:/usr/local/symbiflow/vtr/bin/
+./versa_ecp5.py --sys-clk-freq=100e6 --build  --fpga=artya7100t \
+                    --toolchain=symbiflow
+