+Outstanding issues for 2.0 release:
+--------------------
+1. Fix O3 CPU bug in SE 40.perlbmk fails
+2. Fix O3 processing nacks/coherence messages
+3. Better statistics for the caches.
+4. FS mode doesn't work under Cygwin
+5. memtest regression crashes under Cygwin
+6. Make repository public
+7. Testing
+8. Validation
+
+March 1, 2008: m5_2.0_beta5
+--------------------
+New Features
+1. Rick Strong's Simpoints config changes
+2. Support for FSU ARM port
+3. EXTRAS= option allow architectures to be specified
+
+Bug fixes
+1. Bus timing more realistic
+2. Cache writeback, LL/SC fixes
+3. Minor IGbE NIC fixes
+4. O3 op latency fix
+5. SPARC TLB demap fixes
+6. SPARC SE memory layout fixes
+7. Variety of MIPS fixes
+
+Nov 4, 2007: m5_2.0_beta4
+--------------------
+New Features
+1. New cache model
+2. Use of a I/O cache between devices and memory
+3. Ability to include compiled code with EXTRAS=
+4. Python creation of params structures for initialization
+5. Ability to remotely debug in SE
+
+Bug fixes:
+1. Fix SE serialization
+2. SPARC_FS booting with TimingSimpleCPU
+3. Rename cycles() to ticks()
+4. Various SPARC ISA fixes
+5. Draining code for checkpointing
+6. Various performance improvements
+
+Possible Incompatibilities:
+1. Real TLBs are now used in SE mode. This is more accurate however it could
+ cause some problems if you've modified the way page handling is done in
+ SE mode.
+2. There have been many changes to the way the SCons files work. SimObjects,
+ sources files, and trace flags are all specified in the SConscript files.
+ To see how to add your sources take a look at one of them.
+3. Python is now used to created the parameter structs that were created
+ manually before. The parameters listed in a py file are turned into
+ a header file with the same name (e.g. BadDevice.py -> BadDevice.hh).
+ With this change the structs can be populated automatically and the
+ ugly macros to define and create SimObjects at the bottem of source
+ files are gone. The parameter structs also automatically inherit
+ parameters from their parents.
+
+May 16, 2007: m5_2.0_beta3
+--------------------
+New Features
+1. Some support for SPARC full-system simulation
+2. Reworking of trace facitities (parameter names changed, variadic macros
+ removed)
+3. Scons script cleanups
+4. Some support for compiling with Intel CC
+
+Bug fixes since beta 2:
+1. Many SPARC linux syscall emulation support fixes
+2. Multiprocessor linux boot using the detailed O3 CPU module
+3. Workaround for DMA bug (final solution to be released with 2.0f)
+4. Simulator performance and memory leak fixes
+5. Fixed issue where console could stop printing in ALPHA_FS
+6. Fix issues with remote debugging
+7. Several compile fixes, including gcc 4.1
+8. Many other minor fixes and enhancements
+
+Nov. 28, 2006: m5_2.0_beta2
+--------------------
+Bug fixes since beta 1:
+1. Many cache issues resolved
+2. Uni-coherence fixes in full-system
+3. LL/SC Support
+4. Draining/Switchover
+5. Functional Accesses
+6. Bus now has real timing
+7. Single config file for all SpecCPU2000 benchmarks
+8. Several other minor bug fixes and enhancements
+
Aug. 25, 2006: m5_2.0_beta patch 1
--------------------
Handful of minor bug fixes for m5_2.0_beta,
projects / gem5.git / blobdiff