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[libreriscv.git] / SEP-210803722-Libre-SOC-8-core.mdwn

diff --git a/SEP-210803722-Libre-SOC-8-core.mdwn b/SEP-210803722-Libre-SOC-8-core.mdwn
index 7cfc58237f20d88d77d599b7dee1ac670f7ab02f..0462bcc38a2f865935453effd916796ba8b2b0f3 100644 (file)
--- a/SEP-210803722-Libre-SOC-8-core.mdwn
+++ b/SEP-210803722-Libre-SOC-8-core.mdwn
@@ -8,8 +8,8 @@ List of participants
 |----- |-------------           |---------------------                |---------        |-------------  |
 | 1    |David Calderwood        |RED Semiconductor Ltd                |UK                |1/RED                |
 | 2    |Luke Leighton        |The Libre-SOC Project                        |Netherlands        |2/Libre-SOC        |
-| 3    |Céline Ghibaudo        |Sorbonne Université (LIP6 Lab)        |France                |3/SU                |
-| 4    |Céline Ghibaudo        |Sorbonne Université (CNRS Lab)        |France                |4/CNRS        |
+| 3    |Marie-Minervé Louerat  |Sorbonne Université (LIP6 Lab)        |France                |3/SU                |
+| 4    |Marie-Minervé Louerat  |Sorbonne Université (CNRS Lab)        |France                |4/CNRS        |
 | 5    |Michiel Lenaars        |NLnet                                        |Netherlands        |5/NLnet        |
 | 6    |James Lewis        |Helix Technology Ltd                        |UK                |6/Helix                |
 
@@ -64,7 +64,8 @@ SVP64 contains features and capabilities never seen in any Instruction
 Set Architecture (ISA) of the past sixty years.  With NLnet's help we have
 TRL (3) implementations and simulations demonstrating a 75% reduction in
 the program size of core algorithms for Video and Audio DSP Processing
-(FFT, DCT, Matrix Multiply), and these still need optimized, which if
+(FFT, DCT, Matrix Multiply), and these still have room for optimisation,
+which if
 successfully expanded to general-purpose algorithms would result in huge
 power savings if deployed in mass-volume end-user products.
 
@@ -185,11 +186,11 @@ Grant application will support and will allow LIP6 and CNRS to enhance
 it to lower geometries and larger ASIC sizes which will be critical to
 European businesses' Digital and Silicon Sovereignty.
 
- For the avoidance of confusion the use of the word "Cell" refers to a
+For the avoidance of confusion the use of the word "Cell" refers to a
 bounded piece of electronic design that when used together, like bricks,
 form larger more complicated electrical functions.
 
- To help advance Digital Sovereignty, LIP6 and CNRS need to once
+To help advance Digital Sovereignty, LIP6 and CNRS need to once
 again push the boundaries of the Libre/Open VLSI toolchain, coriolis2
 Place-and-Route, https://coriolis2.lip6.fr and HITAS/YAGLE Static Timing
 Analyser https://www-soc.lip6.fr/equipe-cian/logiciels/tasyagle/ both
@@ -200,7 +201,8 @@ at TRL 2 for lower geometries 90, 65, 45 nm and below.
 Chips4Makers (also NLnet funded) created FlexLib Libre/Open Cell
 Libraries which allows porting of Standard Cell Libraries to any geometry.
 An NDA'd TSMC 180nm version of FlexLib was created for the Libre-SOC
-180nm test ASIC.  To achieve our objectives, LIP6 and CNRS will need to
+180nm test ASIC.  To achieve our objectives, RED Semiconductor,
+Libre-SOC, LIP6 and CNRS will need to
 create smaller geometry ports of FlexLib.  These Cell Libraries need to
 be tested in actual Silicon, and consequently we will be working with
 IMEC as a sub-contractor and partner to deliver MPW Shuttle Runs for
@@ -827,7 +829,7 @@ Work Packages:
 
 #       3.1        Work plan and resources
 
-[[!img 2021-10-19_09-50.png size="650px" ]]
+[[!img 2021-10-19_09-50.png size="550px" ]]
 
 Tables for section 3.1