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[libreriscv.git] / SEP-210803722-Libre-SOC-8-core.mdwn

diff --git a/SEP-210803722-Libre-SOC-8-core.mdwn b/SEP-210803722-Libre-SOC-8-core.mdwn
index 9f8d280666775380071b9f58f2106aec0b561c8e..507b03dd6aec46da32665b282a8778633b1bbfd2 100644 (file)
--- a/SEP-210803722-Libre-SOC-8-core.mdwn
+++ b/SEP-210803722-Libre-SOC-8-core.mdwn
@@ -185,11 +185,11 @@ Grant application will support and will allow LIP6 and CNRS to enhance
 it to lower geometries and larger ASIC sizes which will be critical to
 European businesses' Digital and Silicon Sovereignty.
 
- For the avoidance of confusion the use of the word "Cell" refers to a
+For the avoidance of confusion the use of the word "Cell" refers to a
 bounded piece of electronic design that when used together, like bricks,
 form larger more complicated electrical functions.
 
- To help advance Digital Sovereignty, LIP6 and CNRS need to once
+To help advance Digital Sovereignty, LIP6 and CNRS need to once
 again push the boundaries of the Libre/Open VLSI toolchain, coriolis2
 Place-and-Route, https://coriolis2.lip6.fr and HITAS/YAGLE Static Timing
 Analyser https://www-soc.lip6.fr/equipe-cian/logiciels/tasyagle/ both
@@ -200,7 +200,8 @@ at TRL 2 for lower geometries 90, 65, 45 nm and below.
 Chips4Makers (also NLnet funded) created FlexLib Libre/Open Cell
 Libraries which allows porting of Standard Cell Libraries to any geometry.
 An NDA'd TSMC 180nm version of FlexLib was created for the Libre-SOC
-180nm test ASIC.  To achieve our objectives, LIP6 and CNRS will need to
+180nm test ASIC.  To achieve our objectives, RED Semiconductor,
+Libre-SOC, LIP6 and CNRS will need to
 create smaller geometry ports of FlexLib.  These Cell Libraries need to
 be tested in actual Silicon, and consequently we will be working with
 IMEC as a sub-contractor and partner to deliver MPW Shuttle Runs for