(no commit message)

[libreriscv.git] / The_Mission.mdwn

diff --git a/The_Mission.mdwn b/The_Mission.mdwn
index cb85b412df91957e0c0e6472771053dd277f1942..25879d68181e81316663b12ef79590ece1066a3d 100644 (file)
--- a/The_Mission.mdwn
+++ b/The_Mission.mdwn
@@ -1,23 +1,40 @@
-## The Mission
+> We believe a computer should be safe to use, and this starts with a
+> safe processor.
 
- - give mass volume appliance manufacturers an alternative to expensive un-auditable chips.
- - maximize the degree of trust a customer can place in their processor. 
+# The Mission
 
-## The Means:
+- give mass volume appliance manufacturers an alternative to expensive
+   un-auditable chips.
+- maximize the degree of trust a customer can place in their processor.
 
-- provide the customer the **freedom to study, modify, and redistribute** the full SoC source from HDL and boot loader to down to the VLSI.
-- engage in **full transparency** at every level of the development, right from the inception through to delivery of silicon.  no exceptions.
+# The Means:
 
-## The Market:
+- provide the customer the **freedom to study, modify, and redistribute**
+  the full SoC source from HDL and boot loader to down to the VLSI.
+- engage in **full transparency** at every level of the development,
+  right from the inception through to delivery of silicon.  no exceptions.
+- listen to **constructive input** from world-leading industry experts,
+  engineers and enthusiasts alike, in real-time, without NDAs creating
+  artificial barriers to communication and hampering success.
+
+# The Market:
 
  - chromebooks
  - smartphones
  - tablets
  - industrial boards
  - single-board computers (like the Raspberry Pi)
+ - wearables
+ - CV capable flight controller for lightweight drones
  - whatever you want
 
-## The Machine:
+# The Machines:
+
+- our first target (Oct 2020): a single-core dual-issue 180nm 64-bit
+  "demo" QFP chip that will also be a saleable product in the "Embedded"
+  space (Arduino, STM32F, Ingenic jz4720).
+- a full quad core SoC: 800mhz, dual issue, 4-wide FP32, Hybrid CPU /
+  GPU / VPU [and later an ML inference core], comparable to the Allwinner
+  64 in capability.
+- Products based on customer - and client - driven needs and requirements
 
-- our first target (Oct 2020): a single-core dual-issue 180nm 64-bit "demo" QFP chip that will also be a saleable product in the "Embedded" space (Arduino, STM32F, Ingenic jz4720).
-- a full quad core SoC: 800mhz, dual issue, 4-wide FP32, Hybrid CPU / GPU / VPU [and later an ML inference core], comparable to the Allwinner 64 in capability.