+> We believe a computer should be safe to use, and this starts with a
+> safe processor.
+
# The Mission
- - give mass volume appliance manufacturers an alternative to expensive un-auditable chips.
- - maximize the degree of trust a customer can place in their processor.
+- to give mass volume appliance manufacturers an alternative to expensive
+ un-auditable chips.
+- to maximize the degree of trust a customer (business or user) can place in
+ their processor.
+- to provide a libre, secure and transparently developed hybrid CPU VPU
+ GPU architecture to the world.
+- to provide businesses and users worldwide with an alternative to
+ current proprietary opaque chipsets and drivers.
+
+To accomplish this we:
+
+- use collaborative techniques
+- operate entirely transparently
+- invite developers and experts around the world to contribute without NDAs
+- invite inventors to contribute relevant patents to patent pools (OIN)
# The Means:
-- provide the customer the **freedom to study, modify, and redistribute** the full SoC source from HDL and boot loader to down to the VLSI.
-- engage in **full transparency** at every level of the development, right from the inception through to delivery of silicon. no exceptions.
+- provide the customer the **freedom to study, modify, and redistribute**
+ the full SoC source from HDL and boot loader to down to the VLSI.
+- engage in **full transparency** at every level of the development,
+ right from the inception through to delivery of silicon. no exceptions.
+- listen to **constructive input** from world-leading industry experts,
+ engineers and enthusiasts alike, in real-time, without NDAs creating
+ artificial barriers to communication and hampering success.
# The Market:
- CV capable flight controller for lightweight drones
- whatever you want
-# The Machine:
+# The Machines:
+
+- our first target (Oct 2020): a single-core dual-issue 180nm 64-bit
+ "demo" QFP chip that will also be a saleable product in the "Embedded"
+ space (Arduino, STM32F, Ingenic jz4720).
+- a full quad core SoC: 800mhz, dual issue, 4-wide FP32, Hybrid CPU /
+ GPU / VPU [and later an ML inference core], comparable to the Allwinner
+ 64 in capability.
+- Products based on customer - and client - driven needs and requirements
-- our first target (Oct 2020): a single-core dual-issue 180nm 64-bit "demo" QFP chip that will also be a saleable product in the "Embedded" space (Arduino, STM32F, Ingenic jz4720).
-- a full quad core SoC: 800mhz, dual issue, 4-wide FP32, Hybrid CPU / GPU / VPU [and later an ML inference core], comparable to the Allwinner 64 in capability.