* Experience: FPGA/ASIC system validation, instrument automation using VISA, PCB design (KiCAD, Altium)
* Other interests: Lingua Latina, Philosophy, History
* Availability: Full-time
+* IRC: octavius
## [[Manikandan Nagarajan|Manik]]
-* Languages: Verilog HDL, C, Python & TCL
+* Languages: Verilog HDL, VHDL, C, Python & TCL
* Experience : Domain Specific Architecture Design and Implementation, IP Core Development, System on Chip, FPGA System Design, Chip Tapeout, Crypto Chip Design, Authentication Protocol Design.
* LinkedIn Profile: [[https://www.linkedin.com/in/manikandan-nagarajan-2156171a0/]]
* Availability: 8~10hrs/week