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[libreriscv.git] / about_us.mdwn
index b798f853b4f65c5e0c3123bd7a4ae849687c92c5..3c8345dffa2d203b4ecfd4488332900c276c4e89 100644 (file)
@@ -215,3 +215,11 @@ Alain's website: <http://phcomp.co.uk>
 * Experience: FPGA/ASIC system validation, instrument automation using VISA, PCB design (KiCAD, Altium)
 * Other interests: Lingua Latina, Philosophy, History
 * Availability: Full-time
+* IRC: octavius
+
+## [[Manikandan Nagarajan|Manik]]
+
+* Languages: Verilog HDL, VHDL, C, Python & TCL
+* Experience : Domain Specific Architecture Design and Implementation, IP Core Development, System on Chip, FPGA System Design, Chip Tapeout, Crypto Chip Design, Authentication Protocol Design. 
+* LinkedIn Profile: [[https://www.linkedin.com/in/manikandan-nagarajan-2156171a0/]]
+* Availability: 8~10hrs/week