first pass at merging m5 with linux

[gem5.git] / arch / alpha / alpha_memory.cc

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 4cd1224314046d24a9c9953a86c6b0c255738fad..63fb3ebcbb2e7d916c99a037709fb85ac61e334e 100644 (file)
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -44,20 +44,14 @@ using namespace std;
 //
 //  Alpha TLB
 //
-
-#ifdef DEBUG
-    bool uncacheBit39 = false;
-    bool uncacheBit40 = false;
-#endif
-
-AlphaTlb::AlphaTlb(const string &name, int s)
+AlphaTLB::AlphaTLB(const string &name, int s)
     : SimObject(name), size(s), nlu(0)
 {
     table = new AlphaISA::PTE[size];
     memset(table, 0, sizeof(AlphaISA::PTE[size]));
 }
 
-AlphaTlb::~AlphaTlb()
+AlphaTLB::~AlphaTLB()
 {
     if (table)
         delete [] table;
@@ -65,7 +59,7 @@ AlphaTlb::~AlphaTlb()
 
 // look up an entry in the TLB
 AlphaISA::PTE *
-AlphaTlb::lookup(Addr vpn, uint8_t asn) const
+AlphaTLB::lookup(Addr vpn, uint8_t asn) const
 {
     DPRINTF(TLB, "lookup %#x\n", vpn);
 
@@ -89,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const
 
 
 void
-AlphaTlb::checkCacheability(MemReqPtr &req)
+AlphaTLB::checkCacheability(MemReqPtr &req)
 {
     // in Alpha, cacheability is controlled by upper-level bits of the
     // physical address
@@ -135,7 +129,7 @@ AlphaTlb::checkCacheability(MemReqPtr &req)
 
 // insert a new TLB entry
 void
-AlphaTlb::insert(Addr vaddr, AlphaISA::PTE &pte)
+AlphaTLB::insert(Addr vaddr, AlphaISA::PTE &pte)
 {
     if (table[nlu].valid) {
         Addr oldvpn = table[nlu].tag;
@@ -169,7 +163,7 @@ AlphaTlb::insert(Addr vaddr, AlphaISA::PTE &pte)
 }
 
 void
-AlphaTlb::flushAll()
+AlphaTLB::flushAll()
 {
     memset(table, 0, sizeof(AlphaISA::PTE[size]));
     lookupTable.clear();
@@ -177,7 +171,7 @@ AlphaTlb::flushAll()
 }
 
 void
-AlphaTlb::flushProcesses()
+AlphaTLB::flushProcesses()
 {
     PageTable::iterator i = lookupTable.begin();
     PageTable::iterator end = lookupTable.end();
@@ -197,7 +191,7 @@ AlphaTlb::flushProcesses()
 }
 
 void
-AlphaTlb::flushAddr(Addr vaddr, uint8_t asn)
+AlphaTLB::flushAddr(Addr vaddr, uint8_t asn)
 {
     Addr vpn = VA_VPN(vaddr);
 
@@ -225,7 +219,7 @@ AlphaTlb::flushAddr(Addr vaddr, uint8_t asn)
 
 
 void
-AlphaTlb::serialize(ostream &os)
+AlphaTLB::serialize(ostream &os)
 {
     SERIALIZE_SCALAR(size);
     SERIALIZE_SCALAR(nlu);
@@ -237,7 +231,7 @@ AlphaTlb::serialize(ostream &os)
 }
 
 void
-AlphaTlb::unserialize(Checkpoint *cp, const string &section)
+AlphaTLB::unserialize(Checkpoint *cp, const string &section)
 {
     UNSERIALIZE_SCALAR(size);
     UNSERIALIZE_SCALAR(nlu);
@@ -255,13 +249,13 @@ AlphaTlb::unserialize(Checkpoint *cp, const string &section)
 //
 //  Alpha ITB
 //
-AlphaItb::AlphaItb(const std::string &name, int size)
-    : AlphaTlb(name, size)
+AlphaITB::AlphaITB(const std::string &name, int size)
+    : AlphaTLB(name, size)
 {}
 
 
 void
-AlphaItb::regStats()
+AlphaITB::regStats()
 {
     hits
         .name(name() + ".hits")
@@ -280,7 +274,7 @@ AlphaItb::regStats()
 }
 
 void
-AlphaItb::fault(Addr pc, ExecContext *xc) const
+AlphaITB::fault(Addr pc, ExecContext *xc) const
 {
     uint64_t *ipr = xc->regs.ipr;
 
@@ -293,7 +287,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const
 
 
 Fault
-AlphaItb::translate(MemReqPtr &req) const
+AlphaITB::translate(MemReqPtr &req) const
 {
     InternalProcReg *ipr = req->xc->regs.ipr;
 
@@ -311,7 +305,7 @@ AlphaItb::translate(MemReqPtr &req) const
         if (!validVirtualAddress(req->vaddr)) {
             fault(req->vaddr, req->xc);
             acv++;
-            return Itb_Acv_Fault;
+            return ITB_Acv_Fault;
         }
 
         // Check for "superpage" mapping: when SP<1> is set, and
@@ -373,12 +367,12 @@ AlphaItb::translate(MemReqPtr &req) const
 //
 //  Alpha DTB
 //
-AlphaDtb::AlphaDtb(const std::string &name, int size)
-    : AlphaTlb(name, size)
+AlphaDTB::AlphaDTB(const std::string &name, int size)
+    : AlphaTLB(name, size)
 {}
 
 void
-AlphaDtb::regStats()
+AlphaDTB::regStats()
 {
     read_hits
         .name(name() + ".read_hits")
@@ -447,7 +441,7 @@ AlphaDtb::regStats()
 }
 
 void
-AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
+AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
 {
     uint64_t *ipr = xc->regs.ipr;
 
@@ -471,7 +465,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
 }
 
 Fault
-AlphaDtb::translate(MemReqPtr &req, bool write) const
+AlphaDTB::translate(MemReqPtr &req, bool write) const
 {
     RegFile *regs = &req->xc->regs;
     Addr pc = regs->pc;
@@ -497,7 +491,7 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const
                   req->xc);
 
             if (write) { write_acv++; } else { read_acv++; }
-            return Dtb_Fault_Fault;
+            return DTB_Fault_Fault;
         }
 
         // Check for "superpage" mapping: when SP<1> is set, and
@@ -593,7 +587,7 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const
 }
 
 AlphaISA::PTE &
-AlphaTlb::index(bool advance)
+AlphaTLB::index(bool advance)
 {
     AlphaISA::PTE *pte = &table[nlu];
 
@@ -603,43 +597,45 @@ AlphaTlb::index(bool advance)
     return *pte;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaItb)
+DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
 
     Param<int> size;
 
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaItb)
+END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
 
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaItb)
+BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
 
     INIT_PARAM_DFLT(size, "TLB size", 48)
 
-END_INIT_SIM_OBJECT_PARAMS(AlphaItb)
+END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
 
 
-CREATE_SIM_OBJECT(AlphaItb)
+CREATE_SIM_OBJECT(AlphaITB)
 {
-    return new AlphaItb(getInstanceName(), size);
+    return new AlphaITB(getInstanceName(), size);
 }
 
-REGISTER_SIM_OBJECT("AlphaITB", AlphaItb)
+REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb)
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
 
     Param<int> size;
 
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb)
+END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
 
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDtb)
+BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
 
     INIT_PARAM_DFLT(size, "TLB size", 64)
 
-END_INIT_SIM_OBJECT_PARAMS(AlphaDtb)
+END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
 
 
-CREATE_SIM_OBJECT(AlphaDtb)
+CREATE_SIM_OBJECT(AlphaDTB)
 {
-    return new AlphaDtb(getInstanceName(), size);
+    return new AlphaDTB(getInstanceName(), size);
 }
 
-REGISTER_SIM_OBJECT("AlphaDTB", AlphaDtb)
+REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)